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參數(shù)資料
| 型號： | HCTL-2022 |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quadrature Decoder/Counter Interface ICs |
| 中文描述： | 正交解碼器/計數(shù)器接口芯片 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 302K |
| 代理商： | HCTL-2022 |
12
Digital Noise Filter
The digital noise filter section is
responsible for rejecting noise
on the incoming quadrature
signals. The input section uses
two techniques to implement
improved noise rejection.
Schmitt-trigger inputs and a
three-clock-cycle delay filter
combine to reject low level
noise and large, short duration
noise spikes that typically occur
in motor system applications.
Both common mode and
differential mode noise are
rejected. The user benefits from
these techniques by improved
integrity of the data in the
counter. False counts triggered
by noise are avoided.
Figure 11 shows the simplified
schematic of the input section.
The signals are first passed
through a Schmitt-trigger buffer
to address the problem of input
signals with slow rise times and
low-level noise (approximately <
1V). The cleaned up signals are
then passed to a four-bit delay
filter. The signals on each
channel are sampled on rising
clock edges. A time history of
the signals is stored in the four-
bit shift register. Any change on
the input is tested for a stable
level being present for three
consecutive rising clock edges.
Therefore, the filtered output
waveforms can change only
after an input level has the
same value for three consecutive
rising clock edges.
Refer to Figure 12, which shows
the timing diagram. The result
of this circuitry is that short
noise spikes between rising
clock edges are ignored and
pulses shorter than two clock
periods are rejected.
Figure 11. Simplified Digital Noise Filter Logic
CHA
CHA
filtered
D
Q
D
Q
D
Q
D
Q
CK
CK
J
K
Q
CHB
CHB
filtered
D
Q
D
Q
D
Q
D
Q
CK
CK
J
K
Q
CHI
CHI
filtered
D
Q
D
Q
D
Q
D
Q
CK
CK
J
K
Q
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCTL-2032 | Quadrature Decoder/Counter Interface ICs |
| HCTL-2032-SC | Quadrature Decoder/Counter Interface ICs |
| HCTS00D | Radiation Hardened Quad 2-Input NAND Gate |
| HCTS00HMSR | Radiation Hardened Quad 2-Input NAND Gate |
| HCTS00DMSR | Radiation Hardened Quad 2-Input NAND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCTL-2032 | 功能描述:接口 - 專用 Decoder/Counter RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| HCTL-2032-SC | 功能描述:接口 - 專用 Decoder/Counter RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| HCTL-2032-SCT | 制造商:Avago Technologies 功能描述:QUADRATURE DECODER/ COUNTER INTRFC IC 32PIN - Tape and Reel |
| HCT-L-R5A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| HCT-L-R5B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
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