參數(shù)資料
型號： HCTL-2022
元件分類： 通用總線功能
英文描述： Quadrature Decoder/Counter Interface ICs
中文描述： 正交解碼器/計數(shù)器接口芯片
文件頁數(shù)： 7/20頁
文件大小： 302K
代理商： HCTL-2022
7
Switching Characteristics
Table 5. Switching Characteristics
Max/Min specifications at V
DD
= 5.0
±
5%, T
A
= -40 to +100
O
C, C
L
= 40 pf
Symbol Description
1
t
CLK
Clock Period
2
t
CHH
Pulse width, clock high
3
t
CD
Delay time, rising edge of clock to valid, updated count information on
D0-7
Notes
1.
2.
tclk
max delay (item 20/21) + min delay (item 22/23)
tclk
max delay (item 22/23) + min delay (item 20/21)
Min.
Max.
33
Units
MHz
1/f
ns
31
ns
4
t
ODE
t
ODZ
t
SDV
Delay time, OEN fall to valid data
29
ns
5
Delay time, OEN rise to Hi-Z state on D0-7
29
ns
6
Delay time, SEL0~SEL1 valid to stable, selected data byte (delay to
High Byte = delay to Low Byte)
29
ns
7
t
XNYDV
t
CLH
t
SS
t
OS
t
XNYS
t
SH
t
OH
t
XNYH
t
RST
t
DCD
t
DSD
t
DOD
t
DXNYD
t
UDDX
t
UDDY
t
CHXD
t
CHYD
t
CLXD
t
CLYD
t
UDXH
t
UDYH
t
UDCXS
t
UDCYS
t
UDCXH
t
UDCYH
Delay time, XNY valid to stable, selected data byte.
29
ns
8
Pulse width, clock low
15
ns
9
Setup time, SEL1~SEL2 before clock fall
12
ns
10
Setup time, OEN before clock fall
12
ns
11
Setup time, XNY before clock fall
12
ns
12
Hold time, SEL1~SEL2 after clock fall
0
ns
13
Hold time, OEN after clock fall
0
ns
14
Hold time, XNY after clock fall
0
ns
15
Pulse width, RSTNX~RSTNY low
10
ns
16
Hold time, last position count stable on D0-7 after clock rise
2
ns
17
Hold time, last data byte stable after next SEL state change
2
ns
18
Hold time, data byte stable after OEN rise
2
ns
19
Hold time, data byte stable after XNY change
2
ns
20
Delay time, U/DNX valid after clock rise
4
29
ns
21
Delay time, U/DNY valid after clock rise
4
29
ns
22
Delay time, CNTDECX or CNTCASX high after clock rise
4
31
ns
23
Delay time, CNTDECY or CNTCASY high after clock rise
4
31
ns
24
Delay time, CNTDECX or CNTCASX low after clock fall
4
31
ns
25
Delay time, CNTDECY or CNTCASY low after clock fall
4
31
ns
26
Hold time, U/DNX stable after clock rise
2
ns
27
Hold time, U/DNY stable after clock rise
2
ns
28
Setup time, U/DNX valid before CNTDECX or CNTCASX rise
Note 1
ns
29
Setup time, U/DNY valid before CNTDECY or CNTCASY rise
Note 1
ns
30
Hold time, U/DNX stable after CNTDECX or CNTCASX rise
Note 2
ns
31
Hold time, U/DNY stable after CNTDECY or CNTCASY: rise
Note 2
ns
相關PDF資料
PDF描述
HCTL-2032 Quadrature Decoder/Counter Interface ICs
HCTL-2032-SC Quadrature Decoder/Counter Interface ICs
HCTS00D Radiation Hardened Quad 2-Input NAND Gate
HCTS00HMSR Radiation Hardened Quad 2-Input NAND Gate
HCTS00DMSR Radiation Hardened Quad 2-Input NAND Gate
相關代理商/技術參數(shù)
參數(shù)描述
HCTL-2032 功能描述:接口 - 專用 Decoder/Counter RoHS:否 制造商:Texas Instruments 產品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59
HCTL-2032-SC 功能描述:接口 - 專用 Decoder/Counter RoHS:否 制造商:Texas Instruments 產品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59
HCTL-2032-SCT 制造商:Avago Technologies 功能描述:QUADRATURE DECODER/ COUNTER INTRFC IC 32PIN - Tape and Reel
HCT-L-R5A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
HCT-L-R5B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
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