參數(shù)資料
型號: HD404639R
廠商: Hitachi,Ltd.
英文描述: 4-Bit Single-Chip Microcomputer(4位單片微計算機)
中文描述: 4位單片機(4位單片微計算機)
文件頁數(shù): 17/133頁
文件大?。?/td> 803K
代理商: HD404639R
HD404639R Series
17
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.
The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in
figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.
Program the JMPL instruction at each vector address to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.
Table 2 Vector Addresses and Interrupt Priorities
Reset/Interrupt
RESET,
STOPC
*
INT
0
INT
1
Timer A
Priority
Vector Address
$0000
1
$0002
2
$0004
3
$0006
Timer B, INT
2
Timer C, INT
3
Timer D, INT
4
Serial 1 and 2
Note:
*
The
STOPC
interrupt request is valid only in stop mode
4
$0008
5
$000A
6
$000C
7
$000E
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
INT
0
INT
1
Interrupt Control Bit
Timer A
Timer B
or INT
2
1
Timer C or
INT
3
1
Timer D or
INT
4
1
Serial 1 or
Serial 2
IE
IF0
.
IM0
IF1
.
IM1
IFTA
.
IMTA
IFTB
.
IMTB
+ IF2
.
IM2
IFTC
.
IMTC
+ IF3
.
IM3
IFTD
.
IMTD
+ IF4
.
IM4
IFS1
.
IMS1
+ IFS2
.
IMS2
Note:
*
Can be either 0 or 1. Their values have no effect on operation.
1
1
1
1
1
0
0
0
0
0
0
*
1
0
0
0
0
0
*
*
1
0
0
0
0
*
*
*
1
0
0
0
*
*
*
*
1
0
0
*
*
*
*
*
1
0
*
*
*
*
*
*
1
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