參數(shù)資料
型號: HD404639R
廠商: Hitachi,Ltd.
英文描述: 4-Bit Single-Chip Microcomputer(4位單片微計算機)
中文描述: 4位單片機(4位單片微計算機)
文件頁數(shù): 84/133頁
文件大?。?/td> 803K
代理商: HD404639R
HD404639R Series
84
Operating States:
Serial interface 1 has the following operating states; transitions between them are shown
in figure 67.
STS wait state (serial interface 2 is in SM2A read wait state)
Transmit clock wait state
Transfer state
Continuous clock output state (only in internal clock mode)
System reset
00
SM1A write
04
STS instruction
01
*
Transmit clock
02
Eight transmit clock cycles
STS instruction
(IFS1 1)
03
05
SM1A write
(IFS1 1)
06
STS instruction wait state
(with octal counter = 000,
transmit clock disabled)
Transmit clock wait state
(octal counter = 000)
Transfer state
(octal counter 000)
*
System reset
10
SM1A write
18
SM1A write
14
Transmit clock
17
STS instruction
11
STS instruction
(IFS1 1)
12
Eight transmit clock cycles
STS instruction
(IFS1 1)
13
16
15
*
*
Transmit clock
continuous output state
(PMRA 0, 1 = 00)
Transmit clock wait state
(octal counter = 000)
STS instruction wait state
(with octal counter = 000,
transmit clock disabled)
Transfer state
(octal counter 000)
Note:
Internal Clock Mode
External Clock Mode
*
For serial interface 2, this is accomplished by reading the SM2A register.
Circled numbers are referred to in the text.
Transmit clock
Figure 67 Serial Interface State Transition Diagram
The operation state of serial interface 2 is the same as serial interface 1 except that the STS instruction of
serial interface 1 changes to SM2A read. The following shows the operation state of serial interface 1.
STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 67). In STS
wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then
executed (01, 11), serial interface 1 enters transmit clock wait state.
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參數(shù)描述
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