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參數(shù)資料
| 型號(hào)： | HD404639R |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4-Bit Single-Chip Microcomputer(4位單片微計(jì)算機(jī)) |
| 中文描述： | 4位單片機(jī)（4位單片微計(jì)算機(jī)） |
| 文件頁(yè)數(shù)： | 30/133頁(yè) |
| 文件大小： | 803K |
| 代理商： | HD404639R |
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HD404639R Series
30
Stop mode
Oscillator
Internal
clock
STOP instruction execution
t
res
≥
t
RC
(stabilization period)
t
res
RESET
STOPC
Figure 16 Timing of Stop Mode Cancellation
Subactive Mode:
The OSC
1
and OSC
2
oscillator stops and the MCU operates with a clock generated by
the X1 and X2 oscillator. In this mode, functions other than the DTMF generator operate. However,
because the operating clock is slow, the power dissipation becomes low, next to watch mode.
The CPU instruction execution speed can be selected as 244
μ
s or 122
μ
s by setting bit 2 (SSR12) of
system clock select register 1 (SSR1: $029). Note that the SSR12 value must be changed in active mode.
If the value is changed in subactive mode, the MCU may malfunction.
When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active
mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on
flag (DTON: $020, bit 3).
Subactive mode is an optional function that the user must specify on the function option list.
Interrupt Frame:
In watch and subactive modes,
φ
CLK
is applied to timer A and the
INT
0
circuit.
Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame.
Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure
18).
In watch and subactive modes, the timer-A/
INT
0
interrupt is generated synchronously with the interrupt
frame. The interrupt request is generated synchronously with the interrupt strobe timing except during
transition to active mode. The falling edge of the
INT
0
signal is input asynchronously with the interrupt
frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the
falling edge. An overflow and interrupt request in timer A is generated synchronously with t he interrupt
strobe timing.
Note on Use:
When the MCU is in watch mode or sub-active mode and if the high level period before the
falling edge of
INT
0
is shorter than the interrupt frame or if the low level period after the falling edge of
INT
0
is shorter than the interrupt frame,
INT
0
is not detected. Therefore, the high or low level period of
INT
0
must be held longer than the interrupt frame when the MCU is in watch mode or subactive mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD407A4639R | 4-Bit Single-Chip Microcomputer(4位單片微計(jì)算機(jī)) |
| HD404652 | 4-Bit Single-Chip Microcomputer |
| HD404652H | RES T 0.2E 5W 1% |
| HD404652S | 4-Bit Single-Chip Microcomputer |
| HD404654 | RESISTOR, 0.10 OHM 5W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD404639RF | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:4-Bit Single-Chip Microcomputer |
| HD404639RSERIES | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述: |
| HD404652 | 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:4-Bit Single-Chip Microcomputer |
| HD404652H | 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:4-Bit Single-Chip Microcomputer |
| HD404652S | 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:4-Bit Single-Chip Microcomputer |
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