HD404669 Series
12
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
Port mode register A
Serial mode register 1A
Serial data register 1L
Serial data register 1U
Timer mode register A
Miscellaneous register
Timer mode register C1
Timer C
Timer mode register D1
Timer D
Timer mode register C2
Timer mode register D2
Compare data register
Compare enable register
Tone generator mode register
Tone generator control register
System clock select register 1
System clock select register 2
Data control register D
0
to D
3
Data control register D
4
to D
5
Data control register D
9
to D
11
Data control register R0
Data control register R1
Data control register R2
Data control register R3
Data control register R4
Data control register R6
Data control register R7
Data control register R8
Data control register R9
Data control register RA
V register
Interrupt control bit area
Register flag area
Not used
(PMRA)
(SM1A)
(SR1L)
(SR1U)
(TMA)
(MIS)
(TMC1)
(TRCL/TWCL)
(TRCU/TWCU)
(TMD1)
(TRDL/TWDL)
(TRDU/TWDU)
(TMC2)
(TMD2)
(CDR)
(CER)
(TGM)
(TGC)
(PMRB)
(PMRC)
(ESR1)
(ESR2)
(SM1B)
(SSR1)
(SSR2)
(DCD0)
(DCD1)
(DCD2)
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR6)
(DCR7)
(DCR8)
(DCR9)
(DCRA)
W
W
R/W
R/W
W
W
W
R/W
R/W
W
R/W
R/W
R/W
R/W
R
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
(V)
R/W
(TWCL)
(TWCU)
(TWDL)
(TWDU)
W
W
W
W
R
R
R
R
$000
$260
$3C0
$3FF
RAM-mapped register area
Memory registers
(16 digits)
Data (464 digits x 2)
V = 0 (bank = 0)
V = 1 (bank = 1)
Data (144 digits)
Stack area (64 digits)
R
W
R/W
: Read only
: Write only
: Read/Write
*
1
Not used
RAM address
RAM address
$040
$050
Not
$2F0
$090
Port mode register B
Port mode register C
Detection edge select register 1
Detection edge select register 2
Serial mode register 1B
$00E
$00F
$011
$012
Timer read register CL
Timer read register CU
Timer read register DL
Timer read register DU
(TRCL)
(TRCU)
(TRDL)
(TRDU)
Timer write register CL
Timer write register CU
Timer write register DL
Timer write register DU
$090
$25F
Note :
*
1. There are two data areas, V = 0 (bank 0) and
V = 1 (bank 1)
Data
(464 digits)
V = 0
(bank = 0)
Data
(464 digits)
V = 1
(bank = 1)
*
2.
Two registers are mapped onto the same address ($00E, $00F, $011, $012)
*
2
Not used
Not used
Not used
Not used
Not used
Not used
Not used
*
2
Figure 2 RAM Memory Map