參數(shù)資料
型號: HD404669
廠商: Hitachi,Ltd.
英文描述: Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit(帶雙音多頻電路的低電壓微計算機)
中文描述: 低電壓如同在微機芯片的DTMF產(chǎn)生電路(帶雙音多頻電路的低電壓微計算機)
文件頁數(shù): 25/142頁
文件大小: 894K
代理商: HD404669
HD404669 Series
25
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt
Cuntrol Bit
INT
0
1
INT
1
1
Timer A
INT
2
1
Timer C
or INT
3
1
Timer D
or INT
4
1
Serial 1
IE
IF0 .
IM0
IF1 .
IM1
IFTA .
IMTA
IF2
.
IM2
IFTC .
IMTC
+ IF3
.
IM3
IFTD .
IMTD
+ IF4
.
IM4
IFS1
.
IMS
1
Note:
1
1
1
0
0
0
0
0
0
*
1
0
0
0
0
0
*
*
1
0
0
0
0
*
*
*
1
0
0
0
*
*
*
*
1
0
0
*
*
*
*
*
1
0
*
*
*
*
*
*
1
Bits marked
*
can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
1
2
3
4
5
6
Instruction
execution
IE reset
Interrupt
acceptance
Execution of JMPL
instruction at vector address
Execution of
instruction at
start address
of interrupt
routine
Vector address
generation
Note:
*
*
Stacking
The stack is accessed and the IE reset after the instruction
is executed, even if it is a 2-cycle instruction.
Figure 10 Interrupt Sequence
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