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2.8
Memory Map...................................................................................................................... 46
2.8.1
Memory Map......................................................................................................... 46
2.8.2
LCD RAM Address Relocation ............................................................................ 52
2.9
Application Notes ............................................................................................................... 53
2.9.1
Notes on Data Access............................................................................................ 53
2.9.2
Notes on Bit Manipulation .................................................................................... 55
2.9.3
Notes on Use of the EEPMOV Instruction ........................................................... 61
Section 3
Exception Handling ........................................................................................ 63
3.1
Overview ............................................................................................................................ 63
3.2
Reset ................................................................................................................................... 63
3.2.1
Overview ............................................................................................................... 63
3.2.2
Reset Sequence...................................................................................................... 63
3.2.3
Interrupt Immediately after Reset ......................................................................... 65
3.3
Interrupts ............................................................................................................................ 66
3.3.1
Overview ............................................................................................................... 66
3.3.2
Interrupt Control Registers.................................................................................... 67
3.3.3
External Interrupts................................................................................................. 75
3.3.4
Internal Interrupts.................................................................................................. 76
3.3.5
Interrupt Operations .............................................................................................. 76
3.3.6
Interrupt Response Time ....................................................................................... 81
3.4
Application Notes ............................................................................................................... 81
3.4.1
Notes on Stack Area Use ...................................................................................... 81
3.4.2
Notes on Rewriting Port Mode Registers.............................................................. 82
Section 4
Clock Pulse Generators.................................................................................. 85
4.1
Overview ............................................................................................................................ 85
4.1.1
Block Diagram ...................................................................................................... 85
4.1.2
System Clock and Subclock.................................................................................. 85
4.2
System Clock Generator..................................................................................................... 86
4.3
Subclock Generator ............................................................................................................ 88
4.4
Prescalers............................................................................................................................ 91
4.5
Note on Oscillators ............................................................................................................. 92
Section 5
Power-Down Modes ....................................................................................... 93
5.1
Overview ............................................................................................................................ 93
5.1.1
System Control Registers...................................................................................... 96
5.2
Sleep Mode ......................................................................................................................... 99
5.2.1
Transition to Sleep Mode ...................................................................................... 99
5.2.2
Clearing Sleep Mode ............................................................................................. 99
5.3
Standby Mode .................................................................................................................... 99
5.3.1
Transition to Standby Mode.................................................................................. 99
5.3.2
Clearing Standby Mode ........................................................................................ 100