參數(shù)資料
型號(hào): HD66325A
廠商: Hitachi,Ltd.
英文描述: 64-level Grayscale Driver for the TFT Liquid Crystal Display for XGA Systems(高品質(zhì)TFT LCD的64級(jí)灰度驅(qū)動(dòng)器)
中文描述: 64級(jí)灰度驅(qū)動(dòng)的TFT液晶顯示技術(shù)的XGA系統(tǒng)(高品質(zhì)TFT液晶顯示器的64級(jí)灰度驅(qū)動(dòng)器)
文件頁數(shù): 11/28頁
文件大小: 142K
代理商: HD66325A
HD66325A
11
Operation Timing
1 tcyc (max.)
CL2
IC (NO. 1) data latch
CL1
When SHL = Vcc
512
Dij
POL1, 2
INVALID
INVALID
EIO1
511
510
66
65
64
63
2
1
2
1
INVALID
INVALID
2
1
512
2 tcyc (min.)
511
1 tcyc
Final data
Blanking
period
2 tcyc (min.)
Blanking
period
First next-line data
First next-line data
IC (NO. 2)
IC (NO. 8)
3
1 line
2 tcyc (min.)
Y to Y
384
1
2
3
64
511
512
513
65
66
67
EIO2
(NO. 1)
EIO2
(NO. 8)
Final data
Figure 5 Operation Timing
The high level of the enable-input signal (when SHL = V
CC
: EIO1) is latched at the rising edge of the
data-latch clock signal CL2, and data latching begins after one CL2 signal cycle. Data of 6 bits
×
RGB
×
2 pixels, i.e. 6 outputs are simultaneously latched at the rising edge of the CL2 signal. At the rising
edge of the 64th clock pulse of the CL2 signal, the enable-output signal (when SHL = V
CC
: EIO2) is
driven high, and the operation is automatically halted (the standby state is entered) when latching of
data for 384 outputs is completed. By connecting the EIO2 pin to the next-stage EIO1 pin, the next-
stage IC is activated in the same way.
The data-latch clock signal CL2 does not require a clock-halted period. Two-clock period (min.) after
final-data input in one horizontal period is a blanking period, and data input is invalid in this period.
At least two clocks of the CL2 signal must be input during the high-level period of the CL1 signal.
相關(guān)PDF資料
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HD66326T Multiscan XGA/SXGA High-Quality 64-Gradation TFT Liquid Crystal Driver(TFT LCD驅(qū)動(dòng)器)
HD66330T 64-Level Gray Scale Driver for TFT Liquid Crystal Display(TFT LCD的64級(jí)灰度驅(qū)動(dòng)器)
HD66350T 256-level Grayscale TFT for XGA/SXGA/UXGA Systems(高品質(zhì)TFT LCD的256級(jí)灰度驅(qū)動(dòng)器)
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