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參數(shù)資料
| 型號(hào)： | HD66350T |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 256-level Grayscale TFT for XGA/SXGA/UXGA Systems(高品質(zhì)TFT LCD的256級(jí)灰度驅(qū)動(dòng)器) |
| 中文描述： | 256級(jí)灰度的TFT為吋XGA / SXGA /的UXGA系統(tǒng)（高品質(zhì)TFT液晶顯示器的256級(jí)灰度驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 4/30頁(yè) |
| 文件大?。?/td> | 147K |
| 代理商： | HD66350T |
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HD66350T
4
Internal Block Diagram
CL2
FSL
EIO1
EIO2
POL1
POL2
CL1
SM
OS
D27 to D20,
D17 to D10,
D07 to D00
V
LCD
V
CC
GND
V0, V1, V2,
V3, V4
V5, V6, V7,
V8, V9
Clock control
Negative-polarity
grayscale voltage
Latch address selector
384/402 latch circuits (1)
8 planes
384/402 latch circuits (2)
8 planes
G
g
Positive-polarity
grayscale voltage
Data
inversion
circuit
384/402 decoders
384/402 output amplifier circuits
Y1Y2Y3Y4
Y402
Y384
STPLS
ODD/EVN
TEST
TEST2
Figure 2 Block Diagram
1. Clock control unit
Generates the chip-enable signals (EIO2, EIO1) and controls internal timing signals.
2. Data inversion circuit
Uses the POL1 and POL2 signals to perform data polarity inversion (POL = 1) or non-inversion
(POL = 0) processing of input display data.
3. Latch address selector
Generates latch signals for sequentially latching the input display data. Setting the OS pin enables
the operation of the 384-output driver (OS = 0) or 402-output driver (OS = 1).
4. Latch circuits (1)
402
×
8-bit latch circuits that sequentially latch 6-output
×
8-bit input display data.
5. Latch circuits (2)
Perform latching, in synchronization with CL1, of the 402
×
8-bit data latched by latch circuits (1).
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