
HD66522
11
Block Diagram
Address Management Circuit:
Converts the addresses input via A16–A0 from the system to the addresses
for a memory map of the on-chip RAM. When several LSIs (HD66522s) are used, only the LSI whose
address space, set by pins LS0, LS1, LS2 and SHL, contains the input address, accepts the access from the
system, and enables the inside. The address management circuit enables configuration of the LCD display
system with memory addresses not affected by the connection direction, and reduces burdens of software
and hardware in the system. Refer to the How to Use the LS2, LS1 and LS0 Pins to set pins LS0, LS1, LS2,
and SHL.
Line Counter:
Operates refresh functions. When FLM is high, the counter clears the count value and
generates an address to select the first line in the RAM section. The counter increments its value whenever
CL1 is valid and generates an address to select subsequent lines in the RAM section.
Timing Control Circuit:
This circuit controls arbitration between display access and draw access.
Specifically, it controls access timing while receiving signals FLM, CL1,
CS
,
WE
and
OE
as input. FLM
and CL1 are used to perform refresh (display access), that is, to transfer line data to the liquid crystal
circuit.
CS,
WE
and
OE
are used for the CPU to perform draw operation (draw access), that is, to read and
write display data from and the internal RAM. This circuit also generates a timing signal for the FRC
control circuit to implement four-level grayscale display.
Bidirectional Buffer:
Controls the transfer direction of the display data according to signals from pins
WE
and
OE
in draw operation from the system.
Word Line Decoder:
Decodes duty addresses (A16 to A8) and selects one of 240 lines in the display
RAM section, and activates one-line memory cells in the display RAM section.
Data Line Decoder:
Decodes pin addresses (A7 to A0) and selects a data line in the display RAM section
for the 8-bit memory cells in one-line memory cells activated by the word line decoder.
I/O selector:
Reads and writes 8-bit display data for the memory cells in the RAM section.
Display RAM:
160 * 240 * 2-bit memory cell array. Since the memory is static, display data can be held
without refresh operation during power supply.
FRC Circuit:
Implements FRC (frame rate control) function for four-level grayscale display. For details,
refer to
Half Tone Display
.
Data Latch Circuit (1):
Latches 160-pixel grayscale display data processed by the FRC control circuit
after being read from the display RAM section by refresh operation. This circuit is needed to arbitrate
between display access for performing liquid crystal display and draw access from the CPU.
Data Selector (1):
This circuit selects data from data latch circuit (1).
Data Selector (2):
The display data is generated according to the scanning function signal, FX1 and FX0,
and data from data selector (1).