參數(shù)資料
型號(hào): HD66522
廠商: Hitachi,Ltd.
英文描述: 160-Channel Column Driver with Internal Bit-Map RAM for Reflective Color Display and Grayscale Display(點(diǎn)陣圖形LCD160通道驅(qū)動(dòng)器)
中文描述: 160通道,內(nèi)置欄位為反射式彩色顯示和灰度顯示屏(點(diǎn)陣圖形LCD160通道驅(qū)動(dòng)器地圖RAM驅(qū)動(dòng)器)
文件頁(yè)數(shù): 6/47頁(yè)
文件大?。?/td> 276K
代理商: HD66522
HD66522
6
Pin Description
Classi-
fication Symbol
Power
supply
Pin Name
V
CC
I/O
Number
of Pins
3
Function
V
CC
–GND: logic power supply
V
CC1
, V
CC2
V
CC3
GND1 to
GND5
VCH1
VCH2
GND
5
Ground
Column drive
selecet high-
level
LCD deselect
mid-level
voltage
Column drive
selecet low-level
LSI ID select
switch pin 0,1
and 2
Shift direction
control signal
First line marker I
Data transfer
clock
Scan function
data
Display off
signal
2
VCH–GND: LCD drive circuit power supply and
LCD drive level power supplies. The same level
must be supplied to both pins.
LCD drive level power supplies See Figure 1.
The same level must be supplied to both pins.
VM1
VM2
2
VCL1
VCL2
LS0
LS1
LS2
SHL
2
LCD Column drive selects low-level. The same
level must be supplied to both pins.
Pins for setting LSI ID No (refer to
Pin functions
for details).
Control
signals
I
3
I
1
Reverses the relationship between LCD drive
output pins Y and addresses.
First line select signal.
Clock signal to transfer the line data to an LCD
display driver block.
Scan function data to select LCD driver output
level
Control signal to fix LCD driver outputs to LCD
deselect mid level. When low, LCD drive outputs
Y1 to Y160 are set to VM. Display can be turned
off by setting a common driver to VM.
Setting this pin low initializes the HD66522
Upper 9 bits (A16–A8) are used for the duty-
directional addresses, and lower 8 bits (A7–A0)
for the output-pin directional addresses (refer to
Pin Functions
for details).
Packed-pixel 2-bit/pixel display data transfer
(refer to
Pin Functions
for details).
LSI select signal during draw access (refer to
Pin
Functions
for details).
Write-enable signal during draw access (refer to
Pin Functions
for details).
Output-enable signal during draw access (refer to
Pin Functions
for details).
Status output signal
Each Y outputs one of the three voltage levels
VCH, VM or VCL, depending on the combination
of the FX0 or FX1 signal and data levels.
FLM
CL1
1
1
I
FX0
FX1
DISPOFF
I
2
I
1
RESET
A0 to A16
Reset
Address input
I
I
1
17
Bus
inter-
face
DB0 to DB7
Data
input/output
Chip select
signal
Write enable
signal
Output enable
signal
Wait signal
LCD drive
output
I/O
8
CS
I
1
WE
I
1
OE
I
1
WAIT
Y1 to Y160
O
O
1
160
LCD
drive
output
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