參數(shù)資料
型號(hào): HD66522
廠商: Hitachi,Ltd.
英文描述: 160-Channel Column Driver with Internal Bit-Map RAM for Reflective Color Display and Grayscale Display(點(diǎn)陣圖形LCD160通道驅(qū)動(dòng)器)
中文描述: 160通道,內(nèi)置欄位為反射式彩色顯示和灰度顯示屏(點(diǎn)陣圖形LCD160通道驅(qū)動(dòng)器地圖RAM驅(qū)動(dòng)器)
文件頁(yè)數(shù): 9/47頁(yè)
文件大小: 276K
代理商: HD66522
HD66522
9
Bus Interface
CS
(Input):
The chip select signal. When
CS
is low (active), the system can access the on-chip RAM of
the LSI whose address space, set by LS0, LS1, LS2 and SHL pins, contains the input address. When
CS
is
high, the draw access is disabled.
A0 to A16 (Input):
A bus to transfer addresses during RAM access. Upper nine bits (A16 to A8) are duty-
direction addresses, and lower eight bits (A7 to A0) are output pin-direction addresses.
WAIT
(Output):
This signal outputs low when display access and draw access occur at the same time. The
CPU must wait finishing the bus cycle until this signal goes high. The
WAIT
is in high-impedance
condition while
CS
is high, so this pin must be pulled-up with a resistor outside of the HD66522.
WE
(Input):
The CPU can write display data to the internal RAM while
WE
is low. Only the LSI whose
address space, set by pins LS0, LS1, LS2 and SHL, contains the input address can be written to when
CS
is
low.
OE
(Input):
The CPU can read display data from the internal RAM while
OE
is low. Only the LSI whose
address space, set by pins LS0, LS1, LS2 and SHL, contains the input address can be read from when
CS
is
low.
DB7 to DB0 (Input/Output):
The pin function as data input/output pins. They can accomodate to a data
format with 2 bits/pixcel, which implement packed-pixcel four-level grayscale display.
HD66522 HD66522
HD66522 HD66522
ID=1
H
H
ID=0
ID=2
ID=3
HD66522 HD66522
HD66522 HD66522
ID=5
ID=4
ID=6
ID=7
640
480
LCD panel
L: Low Level H: High Level
LS2 LS1 LS0 ID No. RAM Address Arrangement
L
L
L
0
L
H
L
2
H
L
L
4
H
H
L
6
Upper-side
Left to Right
L
L
H
H
L
H
L
H
H
H
H
H
1
3
5
7
Lower-side
Left to Right
Figure 2 LS Pins and Address Assignment
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