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參數(shù)資料
| 型號(hào)： | HD66760 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 104 X 80-dot Graphics LCD Controller/Driver for 256 Colors |
| 中文描述： | 104 × 80點(diǎn)圖形LCD控制器/驅(qū)動(dòng)器的256色 |
| 文件頁(yè)數(shù)： | 48/105頁(yè) |
| 文件大?。?/td> | 653K |
| 代理商： | HD66760 |
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HD66760
48
a) Basic data-send timing through the clock synchronized serial interface
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCL
SDA
"0" "1" "1" "1" "0"
"1"
ID
RS
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Transfer start
Transfer end
RS RW
Device ID code
1st data
2nd data
Start byte
Status / read data register
b) 1st and 2nd byte assignment
D7
D6
D5
D4
D3
D2
D1
D0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
D7
D6
D5
D4
D3
D2
D1
D0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1st byte
Status / read data register
upper bits
2nd byte
Status / read data register
lower bits
c) Consecutive data-send timing through the clock synchnorized serial interface
SCL
SDA
Start byte
(SR or R00h read)
When status is read, valid data can be read after one dummy read cycle.
Dummy read
(1 byte)
Status or device code
upper bits (1 byte)
Status lower bits
(1 byte)
Status or device code
lower bits(1 byte)
CS*
SDA
Start byte (RS=1)
Dummy read
(5 bytes)
Read data upper bits
(1 byte)
Read data lower bits
(1 byte)
Read data lower bits
(1 byte)
CS*
When GRAM data is read, valid data can be read after five dummy read cycles.
Figure 30b Clock synchronized serial interface data-send sequence
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| HD66766R | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:132 x 176-dot Graphics LCD Controller/Driver for 65K Colors |
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