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參數(shù)資料
| 型號： | HI3-7153J-5 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 10-Bit High Speed Sampling A/D Converter |
| 中文描述： | 8-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP40 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 977K |
| 代理商： | HI3-7153J-5 |
12
HI-7153
Detailed Description
The HI-7153 is an 8 channel high speed 10 bit A/D converter
which achieves throughput rates of 200kHz by use of a Two
Step Flash algorithm. A pipelined operation has been
achieved through the use of switched capacitor techniques
which allows the device to sample a new input voltage while
a conversion is taking place. The 8 channel multiplexer can
be randomly addressed. The HI-7153 requires a single
reference input of +2.5V, which is internally inverted to -
2.5V, thereby allowing an input range of -2.5V to +2.5V. The
ten bits are two’s complement coded. The analog and refer-
ence inputs are internally buffered by high speed CMOS
buffers, which greatly simplifies the external analog drive
requirements for the device.
Analog to Digital
Section The HI-7153 uses a conversion technique which is
generally called a ‘‘Two Step Flash’’ algorithm. This
algorithm enables very fast conversion rates without the
penalty of high power dissipation or high cost. A detailed
functional diagram is presented in Figure 1.
The reference input to the HI-7153 is buffered by a high
speed CMOS amplifier which is used to drive one end of the
resistor string. Another high speed amplifier configured in
the inverting unity gain mode inverts the reference voltage
with respect to analog ground and forces it onto the other
end of the resistor string. Both reference amplifiers are offset
trimmed during manufacturing in order to increase the
accuracy of the HI-7153 and to simplify its usage.
Pin Description
DIP
PIN
SYMBOL
DESCRIPTION
1
V
REF
Reference voltage input (+2.50V)
2
AG
Analog ground reference (0V)
3
A
IN0
Analog input channel 0
4
A
IN1
Analog input channel 1
5
A
IN2
Analog input channel 2
6
A
IN3
Analog input channel 3
7
A
IN4
Analog input channel 4
8
A
IN5
Analog input channel 5
9
A
IN6
Analog input channel 6
10
A
IN7
Analog input channel 7
11
NC
No connect or tie to V+ only
12
TEST
Test pin. Connect to DG for normal operation
13
A0
Mux address input. (LSB) Active high.
14
A1
Mux address input. (LSB) Active high.
15
A2
Mux address input. (MSB) Active high.
16
ALE
Mux address enable. When high, the latch is
transparent. Address data is latched on the
falling edge.
17
WR
Write input. With CS low, starts conversion
when pulsed low; continuous conversions
when kept low.
18
CS
Chip select input. Active low.
19
RD
Read input. With CS low, enables output buff-
ers when pulsed low; outputs updated at the
end of conversion.
20
SMODE
Slow memory mode input. Active high.
21
BUS
Bus select input. High = all outputs enabled
together D0-D9, OVR Low = Outputs enabled
by HBE
22
HBE
Byte select (HBE/LBE) input for 8 bit bus.
High = High byte select, D8 - D9, OVR Low =
Low byte select, D0 - D7
23
CLK
Clock input. TTL compatible.
24
DG
Digital ground (0V)
25
EOC
End-of-conversion status. Pulses high at the
end-of-conversion.
26
HOLD
Start of conversion status. Pulses low at the
start-of-conversion.
27
D0
Bit 0 (LSB)
28
D1
Bit 1
29
D2
Bit 2 Output
30
D3
Bit 3 Data
31
D4
Bit 4 Bits
32
D5
Bit 5
33
D6
Bit 6
34
D7
Bit 7
35
D8
Bit 8
36
D9
Bit 9 (MSB)
37
OVR
Out of Range flag. Valid at end of conversion
when output exceeds full scale.
38
V+
Positive supply voltage input (+5.0V)
39
GND
Ground return for comparators (0V)
40
V-
Negative supply voltage input (-5.0V)
DIP
PIN
SYMBOL
DESCRIPTION
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