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參數(shù)資料
| 型號(hào)： | HI3086JCQ |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 6-Bit, 140 MSPS, Flash A/D Converter |
| 中文描述： | 1-CH 6-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 215K |
| 代理商： | HI3086JCQ |
4-1415
Operating Modes
The HI3086 has two types of operating modes which are selected with Pin 41 (SELECT).
Demux Mode
(See Figures 19, 20, 21).
Set the SELECT pin to V
CC
for this mode. In this mode, the
clock frequency is divided by 2 in the IC, and the data is out-
put after being demultiplexed by this
1
/
2
frequency divided
clock. The
1
/
2
frequency divided clock, which has adequate
setup time and hold time for the output data, is output from
the CLKOUT pin.
When using multiple HI3086 units in parallel in this mode, dif-
ferences in the start timing of the
1
/
2
frequency divided clock
may cause operation as shown in Figures 8 and 9. As a coun-
termeasure, the HI3086 is equipped with a function which
resets the
1
/
2
frequency divided clock. When resetting this
clock, the RESET pulse must be input to the RESET pin. See
the Timing Charts for the RESET pulse input timing. The A/D
converter can operate at f
C
(Min) = 140 MSPS in this mode.
FIGURE 5. INTEGRAL LINEARITY ERROR MEASUREMENT
CIRCUIT DIFFERENTIAL LINEARITY ERROR MEA-
SUREMENT CIRCUIT
NOTE: Where
σ
(LSB) is the deviation of the output codes when the
largest slew rate point is sampled at the clock which has exactly the
same frequency as the analog input signal, the aperture jitter Tai is:
t
AJ
=
σ
/
T
FIGURE 6. APERTURE JITTER MEASUREMENT METHOD
FIGURE 7. ERROR RATE MEASUREMENT CIRCUIT
Test Circuits
(Continued)
A < B A > B
COMPARATOR
A6
TO
A1
B6
TO
B1
B0
A0
HI3086
BUFFER
CONTROLLER
DVM
00...00
TO
11..10
V
IN
6
“0”
6
“1”
-V
+V
S2
S1: ON WHEN A < B
S2: ON WHEN A > B
S1
+
-
V
RT
V
RB
33
32
31
30
29
(LSB)
ν
t
σ
V
IN
CLK
V
IN
CLK
SAMPLING TIMING FLUCTUATION
(= APERTURE JITTER)
-------
=
σ
/
------
x2
π
f
.
SIGNAL
SOURCE
COMPARATOR
A > B
PULSE
COUNTER
SIGNAL
SOURCE
HI3086
LATCH
+
1
/
8
LATCH
A
f
C
4
B
6
4 LSB
2V
P-P
SINE WAVE
-1kHz
V
IN
CLK
CLK
f
C
TABLE 2. OPERATING MODE
OPERATING
MODE
SELECT
MAXIMUM
CONVERSION RATE
DATA OUTPUT
CLOCK OUTPUT
DMUX Mode
V
CC
140 Mbps
Demultiplexed Output 70 Mbps
The input clock is
1
/
2
frequency
divided and output at 70MHz.
Straight Mode
GND
100 Mbps
Straight Output 100 Mbps
The input clock is inverted and
output at 100MHz.
HI3086
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