1
HI3197
10-Bit, 125 MSPS D/A Converter
The HI3197 is a high-speed D/A converter which can
perform the multiplexed input of the two system 10-bit data.
The maximum conversion rate achieves 125 MSPS. The
multiplexed operation is possible by the 1/2 frequency-
divided clock or by halving the frequency of the clock with
the clock frequency divider circuit having the reset pin in
the IC. The data input is TTL; the clock input pin and reset
input pin can select either TTL or PECL according to the
application.
Features
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits
Conversion Rate
125 MSPS (PECL)
100 MSPS (TTL)
Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL
Low Power Consumption . . . . . . . . . . . . . . . 400mW (Typ)
Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . 1.5pVs
Clock, Reset Input Level: TTL and PECL Compatible 2:1
Multiplexed Input Function
1
/
2
Frequency-Divided Clock Output Possible by the Built-
In Clock Frequency Divider Circuit
Voltage Output (50
Load Drive Possible)
Single Power Supply or
±
Dual Power Supplies
Polarity Switching Function of Reset Signal
Applications
LCD
DDS
HDTV
Communications (QPSK, QAM)
Pinout
HI3197 (MQFP)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HI3197JCQ
-20 to 75
48 Ld MQFP/
PQFP
Q48.7x7-S
37
38
39
40
41
42
43
44
45
46
47
481
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
2
3
4
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
RESETN/E
RESETP/E
RESET/T
CLKN/E
CLKP/E
CLK/T
DIV2OUT
DIV2IN
DB0 (LSB)
DB1
DB2
DB3
AGND2
VOCLP
R POLARITY
INV
PS
DGND1
(MSB) DA9
DA8
DA7
DA6
DV
CC1
NC
A
C
V
S
V
R
A
A
A
C
D
C
C
C
C
D
A
D
D
D
D
D
(
(
D
D
D
D
D
Data Sheet
October 1998
File Number
4356.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Copyright
Intersil Corporation 1999