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參數(shù)資料
| 型號： | HI5728INZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/19頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT PAR 250M 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時間： | 35ns |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | 125M |
18
FN4321.5
January 22, 2010
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a
±60 ppm/°C drift coefficient over the full
temperature range of the converter. It is recommended that a
0.1
μF capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin (15)
selects the reference. The internal reference can be selected if
pin 15 is tied low (ground). If an external reference is desired,
then pin 15 should be tied high (to the analog supply voltage)
and the external reference driven into REFIO, pin 23. The full
scale output current of the converter is a function of the voltage
reference used and the value of RSET. IOUT should be within
the 2mA to 20mA range, through operation below 2mA is
possible, with performance degradation.
If the internal reference is used, VFSADJ will equal
approximately 1.16V (pin 22). If an external reference is used,
VFSADJ will equal the external reference. The calculation for
IOUT(Full Scale) is:
If the full scale output current is set to 20mA by using the
internal voltage reference (1.16V) and a 1.86k
Ω R
SET
resistor, then the input coding to output current will resemble
the following:
Outputs
IOUTA and IOUTB (or QOUTA and QOUTB) are
complementary current outputs. The sum of the two currents
is always equal to the full scale output current minus one
LSB. If single ended use is desired, a load resistor can be
used to convert the output current to a voltage. It is
recommended that the unused output be either grounded or
equally terminated. The voltage developed at the output
must not violate the output voltage compliance range of
-0.3V to 1.25V. RLOAD should be chosen so that the desired
output voltage is produced in conjunction with the output full
scale current, which is described above in the ‘Reference’
section. If a known line impedance is to be driven, then the
output load resistor should be chosen to match this
impedance. The output voltage equation is:
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 16
and 17 will be biased at zero volts. It is important to note
here that the negative voltage output compliance range limit
is -300mV, imposing a maximum of 600mVP-P amplitude
with this configuration. The loading as shown in Figure 1 will
result in a 500mV signal at the output of the transformer if
the full scale output current of the DAC is set to 20mA.
VOUT = 2 x IOUT x REQ ,where REQ is ~12.5Ω.
Allowing the center tap to float will result in identical
transformer output, however the output pins of the DAC will
have positive DC offset. The 50
Ω load on the output of the
transformer represents the spectrum analyzer’s input
impedance.
TABLE 1. INPUT CODING vs OUTPUT CURRENT (Per DAC)
INPUT CODE (D9-D0)
IOUTA
(mA)
IOUTB
(mA)
11111 11111
20
0
10000 00000
10
00000 00000
0
20
I
OUT Full Scale
() V
FSADJ RSET
32
×
=
(EQ. 1)
V
OUT
I
OUT
R
LOAD
×
=
(EQ. 2)
PIN 17 (20)
PIN 16 (21)
VOUT = (2 x IOUT x REQ)V
100
Ω
50
Ω
50
Ω
50
Ω
IOUTB (QOUTB)
IOUTA (QOUTA)
FIGURE 42.
HI5728
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