3V Supply, VIH (Note 3) 2.1 3 - V Input Logic" />
參數(shù)資料
型號： HI5728INZ-T
廠商： Intersil
文件頁數(shù)： 18/19頁
文件大?。?/td> 0K
描述： IC DAC 10BIT PAR 250M 48LQFP
標準包裝： 1,000
設置時間： 35ns
位數(shù)： 10
數(shù)據(jù)接口： 并聯(lián)
轉換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： *
采樣率（每秒）： 125M
8
FN4321.5
January 22, 2010
Input Logic High Voltage with
3V Supply, VIH
(Note 3)
2.1
3
-
V
Input Logic Low Voltage with
5V Supply, VIL
(Note 3)
-
0
1.3
V
Input Logic Low Voltage with
3V Supply, VIL
(Note 3)
-
0
0.9
V
Input Logic Current, IIH
-10
-
+10
A
Input Logic Current, IIL
-10
-
+10
A
Digital Input Capacitance, CIN
-5
-
pF
TIMING CHARACTERISTICS (Per Channel)
Data Setup Time, tSU
See Figure 41 (Note 3)
3
-
ns
Data Hold Time, tHLD
See Figure 41 (Note 3)
3
-
ns
Propagation Delay Time, tPD
See Figure 41
-
1
-
ns
CLK Pulse Width, tPW1, tPW2
See Figure 41 (Note 3)
4
-
ns
POWER SUPPLY CHARACTERISTICS
AVDD Power Supply
(Notes 8, 9)
2.7
5.0
5.5
V
DVDD Power Supply
(Notes 8, 9)
2.7
5.0
5.5
V
Analog Supply Current (IAVDD)
(5V or 3V, IOUTFS = 20mA)
-
46
60
mA
(5V or 3V, IOUTFS = 2mA)
-
8
-
mA
Digital Supply Current (IDVDD)
(5V, IOUTFS = Don’t Care) (Note 5)
-
6
10
mA
(3V, IOUTFS = Don’t Care) (Note 5)
-
3
-
mA
Supply Current (IAVDD) Sleep Mode
(5V or 3V, IOUTFS = Don’t Care)
-
3.2
6
mA
Power Dissipation
(5V, IOUTFS = 20mA) (Note 6)
-
330
-
mW
(5V, IOUTFS = 2mA) (Note 6)
-
140
-
mW
(3V, IOUTFS = 20mA) (Note 6)
-
170
-
mW
(3V, IOUTFS = 2mA) (Note 6)
-
54
-
mW
(5V, IOUTFS = 20mA) (Note 10)
-
300
-
mW
(3.3V, IOUTFS = 20mA) (Note 10)
-
150
-
mW
(3V, IOUTFS = 20mA) (Note 10)
-
135
-
mW
Power Supply Rejection
Single Supply (Note 7)
-0.2
-
+0.2
% FSR/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625μA). Ideally the ratio
should be 32.
3. Limits established by characterization and are not production tested.
4. Spectral measurements made with differential coupled transformer and 100% amplitude.
5. Measured with the clock at 50MSPS and the output frequency at 1MHz, both channels.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz, both channels.
8. For operation below 3V, it is recommended that the output current be reduced to 12mA or less to maintain optimum performance. DVDD and AVDD
do not have to be equal.
9. For operation above 125MHz, it is recommended that the power supply be 3.3V or greater. The part is functional with the clock above 125MSPS
and the power supply below 3.3V, but performance is degraded.
10. Measured with the clock at 60MSPS and the output frequency at 10MHz, both channels.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = +25°C for All Typical Values. Data given is
per channel except for “POWER SUPPLY CHARACTERISTICS” on page 8 (Continued)
PARAMETER
TEST CONDITIONS
HI5728IN
TA = -40°C TO +85°C
UNITS
MIN
(Note 11)
TYP
MAX
(Note 11)
HI5728
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