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參數(shù)資料
| 型號： | HI5728INZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/19頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT PAR 250M 48LQFP |
| 標準包裝： | 1,000 |
| 設(shè)置時間： | 35ns |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | 125M |
16
FN4321.5
January 22, 2010
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. The
measurement was done by switching from code 0 to 256, or
quarter scale. Termination impedance was 25Ω due to the
parallel resistance of the output 50Ω and the oscilloscope’s
50Ω input. This also aids the ability to resolve the specified
error band without overdriving the oscilloscope.
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification. This is tested under
the same conditions as “Output Settling Time, (tSETT)” on
Timing Diagrams
FIGURE 39. OUTPUT SETTLING TIME DIAGRAM
FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
D9-D0
IOUT
50%
tSETT
1 LSB ERROR BAND
tPD
V
t(ps)
HEIGHT (H)
WIDTH (W)
GLITCH AREA = 1/2 (H x W)
CLK
D9-D0
IOUT
50%
tPW1
tPW2
tSU
tHLD
tSU
tPD
tHLD
tSETT
HI5728
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