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參數(shù)資料
| 型號(hào)： | HI5960IAZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV D/A 14BIT 130MSPS 28-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 35ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 200mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 剪切帶 (CT) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 130M |
| 其它名稱： | HI5960IAZ-TCT |
8
Definition of Specifications
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Full Scale Gain Drift, is measured by setting the data inputs
to be all logic high (all 1s) and measuring the output voltage
through a known resistance as the temperature is varied
from TMIN to TMAX. It is defined as the maximum deviation
from the value measured at room temperature to the value
measured at either TMIN or TMAX. The units are ppm of FSR
(full scale range) per oC.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through RSET).
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either TMIN or TMAX.
The units are ppm per oC.
Offset Drift, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage through a
known resistance as the temperature is varied from TMIN to
TMAX. It is defined as the maximum deviation from the value
measured at room temperature to the value measured at
either TMIN or TMAX. The units are ppm of FSR (full scale
range) per degree oC.
Offset Error, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage through a
known resistance. Offset error is defined as the maximum
deviation of the output current from a value of 0mA.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. The
measurement is done by switching quarter scale.
Termination impedance was 25
due to the parallel
resistance of the 50
loading on the output and the
oscilloscope’s 50
input. This also aids the ability to resolve
the specified error band without overdriving the oscilloscope.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance should be
chosen such that the voltage developed does not violate the
compliance range.
Power Supply Rejection, is measured using a single power
supply. The supply’s nominal +5V is varied ±10% and the
change in the DAC full scale output is noted.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is
0.707 (-3dB) of its original value.
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification. This is tested using
a single code transition across a major current source.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental signal to the largest
harmonically or non-harmonically related spur within the
specified frequency window.
Total Harmonic Distortion, THD, is the ratio of the RMS
value of the fundamental output signal to the RMS sum of
the first five harmonic components.
Detailed Description
The HI5960 is a 14-bit, current out, CMOS, digital to analog
converter. Its maximum update rate is 130MSPS and can be
powered by either single or dual power supplies in the
recommended range of +3V to +5V. Operation with clock
rates higher than 130MSPS is possible; please contact the
factory for more information. It consumes less than 180mW
of power when using a +5V supply with the data switching at
130MSPS. The architecture is based on a segmented
current source arrangement that reduces glitch by reducing
the amount of current switching at any one time. In previous
architectures that contained all binary weighted current
sources or a binary weighted resistor ladder, the converter
might have a substantially larger amount of current turning
on and off at certain, worst-case transition points such as
midscale and quarter scale transitions. By greatly reducing
the amount of current switching at certain “major” transitions,
the overall glitch of the converter is dramatically reduced,
improving settling time, transient problems, and accuracy.
Digital Inputs and Termination
The HI5960 digital inputs are guaranteed to CMOS levels.
However, TTL compatibility can be achieved by lowering the
supply voltage to 3V due to the digital threshold of the input
buffer being approximately half of the supply voltage. The
internal register is updated on the rising edge of the clock.
To minimize reflections, proper termination should be
implemented. If the lines driving the clock and the digital
inputs are long 50
lines, then 50 termination resistors
should be placed as close to the converter inputs as possible
connected to the digital ground plane (if separate grounds
are used). These termination resistors are not likely needed
as long as the digital waveform source is within a few inches
of the DAC.
Ground Planes
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
HI5960
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