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參數(shù)資料
| 型號： | HI5960IBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV D/A 14BIT 130MSPS 28-SOIC |
| 標準包裝： | 26 |
| 設置時間： | 35ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 200mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 130M |
| 產(chǎn)品目錄頁面： | 1236 (CN2011-ZH PDF) |
4
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to ACOM . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DVDD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
HI5960IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA(oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25
oC for All Typical Values
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Resolution
14
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 8)
-5
±2.5
+5
LSB
Differential Linearity Error, DNL
(Note 8)
-3
±1.5
+3
LSB
Offset Error, IOS
(Note 8)
-0.025
+0.025
% FSR
Offset Drift Coefficient
(Note 8)
-
0.1
-
ppm
FSR/o
Χ
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
-10
±2+10
% FSR
With Internal Reference (Notes 2, 8)
-10
±1+10
% FSR
Full Scale Gain Drift
With External Reference (Note 8)
-
±50
-
ppm
FSR/ο
Χ
With Internal Reference (Note 8)
-
±100
-
ppm
FSR/ο
Χ
Full Scale Output Current, IFS
2-
20
mA
Output Voltage Compliance Range
(Note 3, 8)
-0.3
-
1.25
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK
(Note 3)
130
-
MHz
Output Settling Time, (tSETT)
±0.05% (±8 LSB) (Note 8)
-
35
-
ns
Singlet Glitch Area (Peak Glitch)
RL = 25 (Note 8)
-
5
-
pVs
Output Rise Time
Full Scale Step
-
2.5
-
ns
Output Fall Time
Full Scale Step
-
2.5
-
ns
Output Capacitance
-10
-
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/
√Hz
IOUTFS = 2mA
-
30
-
pA/
√Hz
AC CHARACTERISTICS
+5V Power Supply
Spurious Free Dynamic Range,
SFDR Within a Window
fCLK = 100MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 8)
-
77
-
dBc
fCLK = 100MSPS, fOUT = 5.04MHz, 8MHz Span (Notes 4, 8)
-
97
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz, 8MHz Span (Notes 4, 8)
-
97
-
dBc
HI5960
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