SFDR to Nyquist (fCLK/2)
參數(shù)資料
型號(hào)： HI5960IBZ
廠商： Intersil
文件頁(yè)數(shù)： 9/12頁(yè)
文件大?。?/td> 0K
描述： CONV D/A 14BIT 130MSPS 28-SOIC
標(biāo)準(zhǔn)包裝： 26
設(shè)置時(shí)間： 35ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 200mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 管件
輸出數(shù)目和類(lèi)型： 2 電流，單極
采樣率（每秒）： 130M
產(chǎn)品目錄頁(yè)面： 1236 (CN2011-ZH PDF)
6
+3V Power Supply
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2)
fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 8)
-
48
-
dBc
fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 8)
-
66
-
dBc
fCLK = 130MSPS, fOUT = 5.02MHz (Notes 4, 8)
-
74
-
dBc
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 8)
-
49
-
dBc
fCLK = 100MSPS, fOUT = 20.2MHz (Notes 4, 8)
-
59
-
dBc
fCLK = 100MSPS, fOUT = 5.04MHz (Notes 4, 8)
-
72
-
dBc
fCLK = 100MSPS, fOUT = 2.51MHz (Notes 4, 8)
-
77
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 8)
-
56
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz, T = 25
oC (Notes 4, 8)
68
73
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8)
66
-
dBc
fCLK = 50MSPS, fOUT = 2.51MHz (Notes 4, 8)
-
76
-
dBc
fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 8)
-
79
-
dBc
fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8)
-
78
-
dBc
+3V Power Supply
Multitone Power Ratio
fCLK = 20MSPS, fOUT = 2.0MHz to 2.99MHz, 8 Tones at 110kHz
Spacing (Notes 4, 8)
-75
-
dBc
fCLK = 100MSPS, fOUT = 10MHz to 14.95MHz, 8 Tones at 530kHz
Spacing (Notes 4, 8)
-77
-
dBc
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ
Pin 18 Voltage with Internal Reference
1.13
1.2
1.28
V
Internal Reference Voltage Drift
-
±60
-
ppm
/οΧ
Internal Reference Output Current
Sink/Source Capability
-
±50
-
A
Reference Input Impedance
-1
-
M
Reference Input Multiplying Bandwidth (Note 8)
-
1.4
-
MHz
DIGITAL INPUTS
D11-D0, CLK
Input Logic High Voltage with
5V Supply, VIH
(Note 3)
3.5
5
-
V
Input Logic High Voltage with
3V Supply, VIH
(Note 3)
2.1
3
-
V
Input Logic Low Voltage with
5V Supply, VIL
(Note 3)
-
0
1.3
V
Input Logic Low Voltage with
3V Supply, VIL
(Note 3)
-
0
0.9
V
Sleep Input Current, IIH
-25
-
+25
A
Input Logic Current, IIH
-20
-
+20
A
Input Logic Current, IIL
-10
-
+10
A
Digital Input Capacitance, CIN
-5
-
pF
TIMING CHARACTERISTICS
Data Setup Time, tSU
See Figure 4 (Note 3)
-
1.5
-
ns
Data Hold Time, tHLD
See Figure 4 (Note 3)
-
1.2
-
ns
Propagation Delay Time, tPD
See Figure 4
-
2.5
-
ns
CLK Pulse Width, tPW1, tPW2
See Figure 4 (Note 3)
4
-
ns
Electrical Specifications
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25
oC for All Typical Values (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HI5960
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