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參數(shù)資料
| 型號： | HM-6508883 |
| 廠商： | Intersil Corporation |
| 英文描述： | 1024 x 1 CMOS RAM |
| 中文描述： | 1024 × 1 CMOS存儲器 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 234K |
| 代理商： | HM-6508883 |
6-75
The write cycle is initiated by the falling edge of E which
latches the address information into the on chip registers.
The write portion of the cycle is defined as both E and W
being low simultaneously. W may go low anytime during the
cycle, provided that the write enable pulse setup time
(TWLEH) is met. The write portion of the cycle is terminated
by the first rising edge of either E or W. Data setup and hold
times must be referenced to the terminating signal.
If a series of consecutive write cycles are to be performed,
the W line may remain low until all desired locations have
been written. When this method is used, data setup and hold
times must be referenced to the rising edge of E. By posi-
tioning the W pulse at different times within the E low time
(TELEH), various types of write cycles may be performed.
If the E low time (TELEH) is greater than the W pulse
(TWLWH), plus an output enable time (TELQX), a combina-
tion read write cycle is executed. Data may be modified an
indefinite number of times during any write cycle (TELEH).
The data input and data output pins may be tied together for
use with a common I/O data bus structure. When using the
RAM in this method, allow a minimum of one output disable
time (TWLQZ) after W goes low before applying input data to
the bus. This will ensure that the output buffers are not active.
Test Load Circuit
NOTE:
1. Test head capacitance includes stray and jig capacitance.
TRUTH TABLE
TIME
REFERENCE
INPUTS
OUTPUTS
FUNCTION
E
W
A
D
Q
-1
H
X
X
X
Z
Memory Disabled
0
X
V
X
Z
Cycle Begins, Addresses are Latched
1
L
X
X
Z
Write Period Begins
2
L
X
V
Z
Data is Written
3
H
X
X
Z
Write Completed
4
H
X
X
X
Z
Prepare for Next Cycle (Same as -1)
5
X
V
X
Z
Cycle Ends, Next Cycle Begins (Same as 0)
DUT
1.5V
IOL
IOH
+
(NOTE 1) CL
EQUIVALENT CIRCUIT
HM-6508/883
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