參數(shù)資料
型號(hào): HM-6508
廠商: Intersil Corporation
英文描述: 1024 x 1 CMOS RAM
中文描述: 1024 × 1 CMOS存儲(chǔ)器
文件頁(yè)數(shù): 4/9頁(yè)
文件大?。?/td> 234K
代理商: HM-6508
6-72
TABLE 2. HM-6508/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
GROUP A
SUB-
GROUPS
TEMPERATURE
LIMITS
UNITS
HM-6508B/883
HM-6508/883
MIN
MAX
MIN
MAX
Chip Enable
Access Time
(1) TELQV
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
-
180
-
250
ns
Address Access
Time
(2) TAVQV
VCC = 4.5 and
5.5V, Note 3
9, 10, 11
-55
o
C
T
A
+125
o
C
-
180
-
250
ns
Chip Enable
Output Disable
Time
(3) TELQX
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
5
-
5
-
ns
Write Enable
Output Disable
Time
(4) TWLQZ
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
-
120
-
160
ns
Chip Enable
Output Disable
Time
(5) TEHQZ
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
-
120
-
160
ns
Chip Enable
Pulse Negative
Width
(6) TELEH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
180
-
250
-
ns
Chip Enable
Pulse Positive
Width
(7) TEHEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
100
-
100
-
ns
Address Setup
Time
(8) TAVEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
0
-
0
-
ns
Address Hold
Time
(9) TELAX
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
40
-
50
-
ns
Data Setup Time
(10) TDVWH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
80
-
110
-
ns
Data Hold Time
(11) TWHDX
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
0
-
0
-
ns
Chip Enable
Write Pulse
Setup Time
(12) TWLEH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
100
-
130
-
ns
Chip Enable
Write Pulse Hold
Time
(13) TELWH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
100
-
130
-
ns
Write Enable
Pulse Width
(14) TWLWH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
100
-
130
-
ns
Read or Write
Cycle Time
(15) TELEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
280
-
350
-
ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC -2.0V; Input rise and fall times: 5ns (max); input and output timing reference level: 1.5V; Output load:
1TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
HM-6508/883
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