參數(shù)資料
型號: HM-6508
廠商: Intersil Corporation
英文描述: 1024 x 1 CMOS RAM
中文描述: 1024 × 1 CMOS存儲器
文件頁數(shù): 6/9頁
文件大?。?/td> 234K
代理商: HM-6508
6-74
In the HM-6508/883 Read Cycle, the address information is
latched into the on-chip registers on the falling edge of E
(T = 0). Minimum address setup and hold time requirements
must be met. After the required hold time, the addresses
may change state without affecting device operation. During
time (T = 1) the data output becomes enabled; however, the
data is not valid until during time (T = 2).
W must remain high for the read cycle. After the output data
has been read, E may return high (T = 3). This will disable
the chip and force the output buffer to a high impedance
state. After the required E high time (TEHEL) the RAM is
ready for the next memory cycle (T = 4).
Timing Wavforms
(continued)
TRUTH TABLE
TIME REFERENCE
INPUTS
OUTPUTS
FUNCTION
E
W
A
D
Q
-1
H
X
X
X
Z
Memory Disabled
0
H
V
X
Z
Cycle Begins, Addresses are Latched
1
L
H
X
X
X
Output Enabled
2
L
H
X
X
V
Output Valid
3
H
X
X
V
Read Accomplished
4
H
X
X
X
Z
Prepare for Next Cycle (Same as -1)
5
H
V
X
Z
Cycle Ends, Next Cycle Begins (Same as 0)
TIME
REFERENCE
(8) TAVEL
TELAX
(9)
(8) TAVEL
NEXT
TELEL
TEHEL
(15)
(7)
TELEH
(6)
(7)
TEHEL
TWLEH
(14)
(12)
TWLWH
(13)
VALID DATA INPUT
TELWH
TWHDX (11)
TDVWH
(10)
HIGH 2
-1
0
1
2
3
4
5
A
E
W
D
O
VALID
FIGURE 2. WRITE CYCLE
HM-6508/883
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM-6508/883 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1024 x 1 CMOS RAM
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