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參數(shù)資料
| 型號(hào)： | HM1-6561883 |
| 廠商： | Intersil Corporation |
| 英文描述： | 256 x 4 CMOS RAM |
| 中文描述： | 256 × 4 CMOS存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大?。?/td> | 143K |
| 代理商： | HM1-6561883 |
6-124
is the minimum write pulse. At the end of the write period, if
W rises before either select the outputs will enable reading
data just written. They will not disable until either select goes
high (TSHQZ).
If a series of consecutive write cycles are to be performed,
W may remain low until all desired locations are written. This
is an extension of Case 2.
Read-Modify-Write cycles and Read-Write-Read cycles can
be performed (extension of Case 1). In fact data may be
modified as many times as desired with E remaining low.
Burn-In Circuit
HM-6561/883
CERDIP
NOTES:
All resistors 47k
±
5%.
F0 = 100kHz
±
10%.
F1 = F0
÷
2, F2 = F1
÷
2, F3 = F2
÷
2 . . . F12 = F11
÷
2.
VCC = 5.5V
±
0.5V.
VIH = 4.5V
±
10%.
VIL = -0.2V to +0.4V.
C1 = 0.01
μ
F Min.
IF
OBSERVE
IGNORE
CASE 1
Both S1 and S2 = Low
Before W = Low
TWLQZ
TWLDV
TDVWH
TWLWH
CASE 2
W = Low Before Both
S1 and S2 = Low
TWLWH
TDVWH
TWLQZ
TWLDV
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
VCC
W
S1
DQ3
DQ2
DQ1
DQ0
A4
S2
A3
A2
A1
A0
A5
A6
GND
A7
E
C1
VCC
F6
F5
F4
F3
F8
F9
F10
F0
F7
F1
F0
F2
F2
F2
F2
F0
HM-6561/883
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM1-65787H-2 | HIGH SPEED CMOS SRAM |
| HM3-65787H-2 | HIGH SPEED CMOS SRAM |
| HM4-65787H-2 | HIGH SPEED CMOS SRAM |
| HMT-65787H-2 | HIGH SPEED CMOS SRAM |
| HM1-65787N-2 | HIGH SPEED CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM1-6561-9 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HM1-6561B/883 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:256 x 4 CMOS RAM |
| HM1-6561B883 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:256 x 4 CMOS RAM |
| HM1-6561B-9 | 制造商:Harris Corporation 功能描述: 制造商:MHS>Matra Harris Semi 功能描述: 制造商:Harris Corporation 功能描述:Synchronous SRAM, 256 x 4, 18 Pin, Ceramic, DIP |
| HM1-6562B-8 | 制造商:Harris Corporation 功能描述:1-6562B-8 |
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