參數(shù)資料
型號: HM1-6561B883
廠商: Intersil Corporation
英文描述: 256 x 4 CMOS RAM
中文描述: 256 × 4 CMOS存儲器
文件頁數(shù): 1/9頁
文件大?。?/td> 143K
代理商: HM1-6561B883
6-117
March 1997
HM-6561/883
256 x 4 CMOS RAM
Features
This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Low Power Standby. . . . . . . . . . . . . . . . . . . . 50
μ
W Max
Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
Fast Access Time. . . . . . . . . . . . . . . . . . . . . .200ns Max
Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
TTL Compatible Input/Output
High Output Drive - 1 TTL Load
On-Chip Address Registers
Common Data In/Out
Three-State Output
Easy Microprocessor Interfacing
Description
The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high per-
formance and low power operation.
On-chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays. The data inputs
and outputs are multiplexed internally for common I/O bus
compatibility.
The HM-6561/883 is a fully static RAM and may be
maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Ordering Information
Pinout
HM-6561/883 (CERDIP)
TOP VIEW
PACKAGE
TEMPERATURE RANGE
-55
o
C to +125
o
C
220ns
300ns
PKG. NO.
CERDIP
HM1-6561B/883
HM1-6561/883
F18.3
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W
Write Enable
S
Chip Select
DQ
Data In/Out
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
VCC
W
S1
DQ3
DQ2
DQ1
DQ0
A4
S2
A3
A2
A1
A0
A5
A6
GND
A7
E
File Number
2990.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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