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參數(shù)資料
| 型號： | HM1-6561B883 |
| 廠商： | Intersil Corporation |
| 英文描述： | 256 x 4 CMOS RAM |
| 中文描述： | 256 × 4 CMOS存儲器 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 143K |
| 代理商： | HM1-6561B883 |
6-123
Timing Waveforms
(Continued)
The write cycle begins with the E falling edge latching the
address. The write portion of the cycle is defined by E, S1,
S2 and W all being low simultaneously. The write portion of
the cycle is terminated by the first rising edge of any control
line, E, S1, S2 or W. The data setup and data hold times
(TDVWH and TWHDX) must be referenced to the terminat-
ing signal. For example, if S2 rises first, data setup and hold
times become TDVS2H and TS2HDX; and are numerically
equal to TDVWH and TWHDX.
Data input/output multiplexing is controlled by W. Care must
be taken to avoid data bus conflicts, where the RAM outputs
become enabled when another device is driving the data
inputs. The following two examples illustrate the timing
required to avoid bus conflicts.
Case 1: Both S1 and S2 Fall Before W Falls.
If both selects fall before W falls, the RAM outputs will
become enabled. W is used to disable the outputs, so a dis-
able time (TWLQZ = TWLDV) must pass before any other
device can begin to drive the data inputs. This method of
operation requires a wider write pulse, because TWLDV +
TDVWH is greater than TWLWH. In this case TWLSL +
TSHWH are meaningless and can be ignored.
Case 2: W Falls Before Both S1 and S2 Fall.
If one or both selects are high until W falls, the outputs are
guaranteed not to enable at the beginning of the cycle. This
eliminates the concern for data bus conflicts and simplifies
data input timing. Data input may be applied as early as
convenient, and TWLDV is ignored. Since W is not used to
disable the outputs it can be shorter than in Case 1; TWLWH
(7) TAVEL
(8)
VALID
(7) TAVEL
TELAX
NEXT
(11) TWLDV
(10) TWHDX
VALID DATA
A
E
DQ
S1, S2
TIME
W
REFERENCE
-1
0
1
2
3
4
5
(17) TELEL
(5) TELEH
(6) TEHEL
(6) TEHEL
(13) TWLEH
(15) TELWH
(16) TWLWH
(14) TSLWH
(12) TWLSH
FIGURE 2. WRITE CYCLE
(9) TDVWH
TRUTH TABLE
TIME
REFERENCE
INPUTS
FUNCTION
E
S1
W
A
DQ
-1
H
H
X
X
X
Memory Disabled
0
X
X
V
X
Cycle Begins, Addresses are Latched
1
L
L
L
X
X
Write Period Begins
2
L
L
X
V
Data In is Written
3
X
H
X
X
Write is Completed
4
H
H
X
X
X
Prepare for Next Cycle (Same as -1)
5
X
X
V
X
Cycle Ends, Next Cycle Begins (Same as 0)
NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
HM-6561/883
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| HM-6561 | 256 x 4 CMOS RAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HM1-6561B-9 | 制造商:Harris Corporation 功能描述: 制造商:MHS>Matra Harris Semi 功能描述: 制造商:Harris Corporation 功能描述:Synchronous SRAM, 256 x 4, 18 Pin, Ceramic, DIP |
| HM1-6562B-8 | 制造商:Harris Corporation 功能描述:1-6562B-8 |
| HM1-65641-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HM1-65641-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HM1-65641-5+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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