參數(shù)資料
型號： HM5257805BTD-75
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
中文描述： 64M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù)： 17/62頁
文件大小： 463K
代理商： HM5257805BTD-75
HM5257165B/HM5257805B/HM5257405B-75/A6
Data Sheet E0081H10
17
From PRECHARGE state, command operation
To [DESL], [NOP]:
When these commands are executed, the SDRAM enters the IDLE state after t
RP
has
elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [PRE] or [PALL]:
These commands result in no operation.
To [ACTV]:
The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]:
The SDRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]:
The synchronous DRAM enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP]:
These commands result in no operation.
To [READ], [READ A]:
A read operation starts. (However, an interval of t
RCD
is required.)
To [WRIT], [WRIT A]:
A write operation starts. (However, an interval of t
RCD
is required.)
To [ACTV]:
This command makes the other bank active. (However, an interval of t
RRD
is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]:
These commands set the SDRAM to precharge mode. (However, an interval of t
RAS
is
required.)
From READ state, command operation
To [DESL], [NOP]:
These commands continue read operations until the burst operation is completed.
To [READ], [READ A]:
Data output by the previous read command continues to be output. After
CAS
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]:
These commands stop a burst read, and start a write cycle.
To [ACTV]:
This command makes other banks bank active. (However, an interval of t
RRD
is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]:
These commands stop a burst read, and the SDRAM enters precharge mode.
相關(guān)PDF資料
PDF描述
HM5257805BTD-A6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5259405B-A6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5259165B 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5259165B-75 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5259165B-A6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM5257805BTD-A6 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5259165B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5259165B-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5259165B-A6 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5259165BTD-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
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