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參數(shù)資料
| 型號： | HM5259805BTD-75 |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| 中文描述： | 64M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 20/63頁 |
| 文件大?。?/td> | 368K |
| 代理商： | HM5259805BTD-75 |
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HM5259165B/HM5259805B/HM5259405B-75/A6
Data Sheet E0118H10
20
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A12, BA0 and BA1) during mode register set
cycles. The mode register consists of five sections, each of which is assigned to address pins.
BA1, BA0, A11, A10, A12, A9, A8: (OPCODE):
The SDRAM has two types of write modes. One is the
burst write mode, and the other is the single write mode. These bits specify write mode.
Burst read and burst write:
Burst write is performed for the specified burst length starting from the column
address specified in the write cycle.
Burst read and single write:
Data is only written to the column address specified during the write cycle,
regardless of the burst length.
A7:
Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE):
These pins specify the
CAS
latency.
A3: (BT):
A burst type is specified.
A2, A1, A0: (BL):
These pins specify the burst length.
A2 A1
A0
Burst length
BT=0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
2
4
8
R
R
1
1
1
BT=1
1
1
0
R
R
1
2
4
8
R
R
R
R
A3
0 Sequential
1
Interleave
Burst type
A6
A5
A4 CAS latency
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
R
R
2
3
R
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OPCODE
0
LMODE
BT
BL
A9
0
0
1
1
R
Write mode
A8
0
1
0
1
Burst read and burst write
Burst read and single write
R
R is Reserved (inhibit)
X: 0 or 1
A11
A10
A10
X
X
X
A11
0
X
X
X
0
A12
BA0
BA1
BA1 BA0
0
X
X
X
0
X
X
X
A12
0
X
X
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5259805BTD-A6 | 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5259805B-75 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; Number of Contacts:30; Connector Shell Size:18; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| HM5259405B-75 | Circular Connector; Body Material:Aluminum; Series:PT06; No. of Contacts:30; Connector Shell Size:18; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Circular Contact Gender:Socket; Insert Arrangement:18-30 |
| HM5259805B-A6 | PT 32C 32#20 PIN PLUG |
| HM5264405D | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5259805BTD-A6 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5264165 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HM5264805 HM52654405 Series Synchronous Dynamic RAM |
| HM5264165-10 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| HM5264165A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264165B60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
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