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參數(shù)資料
| 型號： | HM5264165A60 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| 中文描述： | 6400 LVTTL接口SDRAM的133 MHz/100 MHz的 |
| 文件頁數(shù)： | 20/67頁 |
| 文件大小： | 870K |
| 代理商： | HM5264165A60 |
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HM5264165F/HM5264805F/HM5264405F-75/A60/B60
20
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The
mode register consists of five sections, each of which is assigned to address pins.
A13, A12, A11, A10, A9, A8: (OPCODE):
The SDRAM has two types of write modes. One is the burst
write mode, and the other is the single write mode. These bits specify write mode.
Burst read and burst write:
Burst write is performed for the specified burst length starting from the column
address specified in the write cycle.
Burst read and single write:
Data is only written to the column address specified during the write cycle,
regardless of the burst length.
A7:
Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE):
These pins specify the
CAS
latency.
A3: (BT):
A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
A2, A1, A0: (BL):
These pins specify the burst length.
A2 A1
A0
Burst length
BT=0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
2
4
8
R
R
1
1
1
F.P.
BT=1
1
1
0
R
1
2
4
8
R
R
R
R
A3
0 Sequential
1
Interleave
Burst type
A6
0
0
0
0
1
A5
0
0
1
1
X
A4 CAS latency
0
1
0
1
X
R
R
2
3
R
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OPCODE
0
LMODE
BT
BL
A9
0
0
1
1
R
Write mode
Burst read and burst write
A8
0
1
0
1
Burst read and single write
R
F.P. = Full Page
R is Reserved (inhibit)
X: 0 or 1
A11
A10
A10
X
X
X
A11
0
X
X
X
0
A12
A13
A13
0
X
X
X
A12
0
X
X
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5264165B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264165FTT-75 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805FTT-75 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264405FTT-75 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264165FTT-A60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5264165B60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264165D-B60/4805D-B60/4405D-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64M LVTTL Interface SDRAM 100 MHz 1-Mword X 1 |
| HM5264165DLTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HM5264165DLTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HM5264165DTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
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