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參數(shù)資料
| 型號(hào)： | HM530281R |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 331,776-word x 8-bit Frame Memory |
| 中文描述： | 331776字× 8位幀存儲(chǔ)器 |
| 文件頁數(shù)： | 11/47頁 |
| 文件大?。?/td> | 311K |
| 代理商： | HM530281R |
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Datasheet Title
11
Memory Structure
The memory is organized as 331,776-word of 8-bit each, and these words can be accessed sequentially,
since the address pointer can be incremented by inputting a clock signal. Addresses are allocated
corresponding to 32 word blocks.
The mode pins switch between the three addressing modes shown below.
Mode 0
Mode 1
Addressing Mode
Address Structure
Capacity
0
0
1 dim. add. (FIFO)
0 to 10,367 blocks
331,776 words
1
0
2 dim. add. (1)
32 horizontal blocks by 324
vertical lines
1024 dots by 324 lines
0
1
2 dim. add. (2)
36 horizontal blocks by 288
vertical lines
1152 dots by 288 lines
Notes: 1. In 1 dimensional addressing mode, blocks 0 to 10367 are accessed cyclically.
2. In the 2 dimensional addressing modes, the line head can be reset at an arbitrary dot on each
line.
Operations
Write
Write operation:
When the
WE
and
CGW
inputs are low, 8 bits of write data are input in synchronization
with the WCK clock. The input data is read in to the word indicated by the address pointer on the next
rising edge of the WCK cycle. This allows read data and write data to be handled with the same clock, and
cascade connections to be easily implemented.
Write reset operations:
When
CGW
is low, by setting
WRS
low, the write address pointer can be set
immediately on that WCK cycle to the address 0 block head. This operation can be executed independently
of the input level of
WE
. (See ‘Notes on usage’ 15 on the operation when
CGW
is high.)
Write address pointer increment operations:
The write address pointer is incremented in
synchronization with WCK when
CGW
is low. It is possible to apply a write mask in WCK clock units by
setting the
WE
input high. In this case, the previous memory data will be retained. The write address
pointer increment function can be stopped by setting the
CGW
input high. This allows time axis
compression to be implemented easily. (See ‘Notes on usage’ 7, 9 and 10 for interval specifications of
write system reset operations.
*1
)
Note: 1. The write system reset operation stands for write reset, write jump, write window reset, write
line reset and write clear.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM530281RTT-20 | 331,776-word x 8-bit Frame Memory |
| HM530281RTT-25 | 331,776-word x 8-bit Frame Memory |
| HM530281RTT-34 | 331,776-word x 8-bit Frame Memory |
| HM530281RTT-45 | 331,776-word x 8-bit Frame Memory |
| HM530281TT-20 | 331,776 WORD X 8 BIT FRAME MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM530281RTT-20 | 制造商:Hitachi 功能描述:FIELD/FRAME/LINE MEMORY, 44 Pin, Plastic, TSOP |
| HM530281RTT-25 | 制造商:Renesas Electronics Corporation 功能描述:2.5M FRAME RAM (VIDEO) 25NS |
| HM530281RTT-34 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776-word x 8-bit Frame Memory |
| HM530281RTT-45 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776-word x 8-bit Frame Memory |
| HM530281TT | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776 WORD X 8 BIT FRAME MEMORY |
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