參數(shù)資料
型號： HM530281R
廠商： Hitachi,Ltd.
英文描述： 331,776-word x 8-bit Frame Memory
中文描述： 331776字× 8位幀存儲器
文件頁數(shù)： 13/47頁
文件大?。?/td> 311K
代理商： HM530281R
Datasheet Title
13
data at the last dot (address) on each line, address pointer incrementing is stopped. Access is restarted at
either the first dot at the head of the next line or at the first dot at the head of the current line by executing
either a line increment or a line hold, respectively. Also, since these line reset operations can be executed
at any arbitrary point in the middle of a line, an arbitrary line length (of between 64 dots and the actual line
length) can be realized.
Line increment operation:
In case clock gate signal (
CGW
,
CGR
) is low, the read and write line
increment operations are executed by setting
RLRS
low and
RRS
high, and setting
WLRS
low and
WRS
high respectively. When these operations are executed, the next access goes immediately to the starting dot
of the next line.
Line hold operation:
In case clock gate signal (
CGW
,
CGR
) is low, the read and write line hold
operations are executed by setting
RLRS
and
RRS
low, and setting
WLRS
and
WRS
low respectively.
When these operations are executed, the next access goes immediately to the starting dot of the current line.
Note that the read line hold operation is invalid on the first line following a 0 reset or jump. In this case,
the same effect can be achieved by re-executing the reset or jump operation (resetting only the H address to
0). If the reset interval specifications are met (see Notes on Usage 1 to 3), the line reset operation can be
performed on an arbitrary RCK/WCK clock cycle without regard for the levels of the
OE
and
WE
inputs.
(See ‘Notes on usage’ 15 and 16 on the operation when clock gate signal (
CGW
,
CGR
) is high.)
Jump (independent functions for read and write)
It is possible to set the address pointer to the start address of an arbitrary block in 32 word units. After
initializing a jump address setup for read and/or write, after 64 WCK or 64 RCK cycles, it is possible to
execute a jump to that address (random access in 32 word by 8 bit units) independently for read and write.
(See ‘Notes on usage’ 12 on the jump operation to ‘0’ address and line end address.)
Jump address setup:
The read and write jump addresses are serially input independently from the RAD
and WAD pins in synchronization with the RCK and WCK clock inputs respectively. Address input start is
enabled by setting the
RAS
and/or
WAS
inputs low for read and write respectively, and 14/15 bits of jump
address are input sequentially starting with that cycle.
*10
Note that the read and write operations can
continue independently of this address input operation. Jump address setup is executed regardless of
WE
,
CGW
and
OE
,
CGR
. Following the start of address input, it is possible to mask the input of address bits
below an arbitrary bit position by returning
RAS
or
WAS
to the high level at the desired bit position. This
can be convenient in applications that need to jump a fixed interval, since the low order bits of the address
will be fixed. When all 14 bits of an address are to be input, be sure to hold
RAS
and
WAS
low for the full
14-clock period.
Jump operation:
In case clock gate signal (
CGW
,
CGR
) is ‘L’, the jump operation is executed by setting
RRS
and
RAS
low for read, and by setting
WRS
and
WAS
low for write, and the address set is accessed
immediately from that RCK or WCK cycle. Note that as long as the interval specifications listed in Notes
7 to 9 are met, the jump operation can be executed on any RCK or WCK cycle without regard for the
values of
OE
and
WE
. (See ‘Notes on usage’ 14 and 15 on the operation, when clock gate signal (
CGW
,
CGR
) is high.)
相關(guān)PDF資料
PDF描述
HM530281RTT-20 331,776-word x 8-bit Frame Memory
HM530281RTT-25 331,776-word x 8-bit Frame Memory
HM530281RTT-34 331,776-word x 8-bit Frame Memory
HM530281RTT-45 331,776-word x 8-bit Frame Memory
HM530281TT-20 331,776 WORD X 8 BIT FRAME MEMORY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM530281RTT-20 制造商:Hitachi 功能描述:FIELD/FRAME/LINE MEMORY, 44 Pin, Plastic, TSOP
HM530281RTT-25 制造商:Renesas Electronics Corporation 功能描述:2.5M FRAME RAM (VIDEO) 25NS
HM530281RTT-34 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776-word x 8-bit Frame Memory
HM530281RTT-45 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776-word x 8-bit Frame Memory
HM530281TT 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:331,776 WORD X 8 BIT FRAME MEMORY
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