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參數(shù)資料
| 型號： | HM5425161B |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 256M SSTL_2 interface DDR SDRAM(256M SSTL_2接口 DDR 同步DRAM) |
| 中文描述： | 256M DDR SDRAM的接口SSTL_2（256M SSTL_2接口的DDR同步DRAM）的 |
| 文件頁數(shù)： | 48/62頁 |
| 文件大?。?/td> | 1016K |
| 代理商： | HM5425161B |
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HM5425161B, HM5425801B, HM5425401B Series
48
Notes. 1. On all AC measurements, we assume the test conditions shown in the next page. For timing
parameter definitions, see ‘Timing Waveforms’ section.
2. This parameter defines the signal transition delay from the cross point of CLK and
CLK
. The signal
transition is defined to occur when the signal level crossing V
TT
.
3. The timing reference level is V
TT
.
4. Output valid window is defined to be the period between two successive transition of data out or
DQS (read) signals. The signal transition is defined to occur when the signal level crossing V
TT
.
5. t
is defined as Dout transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CLK and
CLK
. This parameter is not referred to a specific Dout
voltage level, but specify when the device output stops driving.
6. t
is defined as Dout transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific Dout voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or
DQS (write) signals. The signal transition is defined to occur when the signal level crossing V
REF
.
8. The timing reference level is V
REF
.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A
specific reference voltage to judge this transition is not given.
10.t
max is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is
not assured.
11.V
is assumed to be 2.5 V
±
0.2 V. V
CC
power supply variation per cycle expected to be less than
0.4 V/400 cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5425161B/801B/401B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Series 256M SSTL-2 Interface DDR SDRAM 143 MHz/133 MHz/125 |
| HM5425161BTT-10 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
| HM5425161BTT-75A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
| HM5425161BTT-75B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
| HM5425401B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
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