參數(shù)資料
型號: HM62V16256B
廠商: Hitachi,Ltd.
英文描述: 4 M SRAM (256-kword ×16-bit)(4 M 靜態(tài)RAM(256k字×16位))
中文描述: 四米的SRAM(256 - KWord的× 16位)(4個M靜態(tài)隨機(jī)存儲器(256k字× 16位))
文件頁數(shù): 7/17頁
文件大?。?/td> 78K
代理商: HM62V16256B
HM62V16256B Series
7
AC Characteristics
(Ta = 0 to +70
°
C, V
CC
= 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
Input pulse levels: V
IL
= 0.4 V, V
IH
= 2.2 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.4 V
Output timing reference levels: 1.4 V
Output load: 1 TTL + 30 pF (HM62V16256B-7) (Including scope and jig)
1 TTL + 100 pF (HM62V16256B-8) (Including scope and jig)
Read Cycle
HM62V16256B
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read cycle time
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
OH
t
BA
t
CLZ1
t
CLZ2
t
BLZ
t
OLZ
t
CHZ1
t
CHZ2
t
BHZ
t
OHZ
70
85
ns
Address access time
70
85
ns
Chip select access time
70
85
ns
70
85
ns
Output enable to output valid
40
45
ns
Output hold from address change
LB
,
UB
access time
10
10
ns
70
85
ns
Chip select to output in low-Z
10
10
ns
2, 3
10
10
ns
2, 3
LB
,
UB
enable to low-z
5
5
ns
2, 3
Output enable to output in low-Z
5
5
ns
2, 3
Chip deselect to output in high-Z
0
25
0
25
ns
1, 2, 3
0
25
0
25
ns
1, 2, 3
LB
,
UB
disable to high-Z
0
25
0
25
ns
1, 2, 3
Output disable to output in high-Z
0
25
0
25
ns
1, 2, 3
相關(guān)PDF資料
PDF描述
HM62V16256CBPI 4 M SRAM (256-kword ×16-bit)(4M靜態(tài)RAM (256k字 ×16位))
HM62V16256CI Wide Temperature Range Version4 M SRAM (256-kword x 16-bit)
HM62V16256CLTTI-7 Wide Temperature Range Version4 M SRAM (256-kword x 16-bit)
HM62V16256CLBP-5 4 M SRAM (256-kword x16-bit)
HM62V16256CLBP-5SL 4 M SRAM (256-kword x16-bit)
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