參數(shù)資料
型號(hào)： HM62V8512B
廠商： Hitachi,Ltd.
英文描述： Quadruple Bus Buffer Gate With 3-State Outputs 14-SOIC -40 to 85
中文描述： 四米的SRAM（512 - KWord的× 8位）
文件頁(yè)數(shù)： 12/17頁(yè)
文件大小： 77K
代理商： HM62V8512B
HM62V8512B Series
12
Low V
CC
Data Retention Characteristics
(Ta = –20 to +70
°
C)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions*
4
CS
≥
V
CC
– 0.2 V, Vin
≥
0 V
V
CC
= 3.0 V, Vin
≥
0 V
CS
≥
V
CC
– 0.2 V
V
CC
for data retention
Data retention current
V
DR
I
CCDR
2
—
—
V
—
0.8*
5
20*
1
μ
A
—
0.8*
5
10*
2
μ
A
μ
A
—
0.8*
5
2*
3
Chip deselect to data retention time
t
CDR
t
R
0
—
—
ns
See retention waveform
Operation recovery time
Notes: 1. For L-version and 10
μ
A (max.) at Ta = –20 to +40
°
C.
2. For L-SL-version and 3
μ
A (max.) at Ta = –20 to +40
°
C.
3. For L-UL-version and 2
μ
A (max.) at Ta = –20 to +40
°
C.
4.
CS
controls address buffer,
WE
buffer,
OE
buffer, and Din buffer. In data retention mode, Vin
levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
5. Typical values are at V
CC
= 3.0 V, Ta = +25
°
C and specified loading, and not guaranteed.
6. t
RC
= read cycle time.
t
RC
*
6
—
—
ns
Low V
CC
Data Retention Timing Waveform
(
CS
Controlled)
CC
V
2.7 V
2.0 V
0 V
CS
t
CDR
t
R
CS V – 0.2 V
DR
V
Data retention mode
相關(guān)PDF資料
PDF描述
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