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參數資料
| 型號： | HM62V8512B |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Quadruple Bus Buffer Gate With 3-State Outputs 14-SOIC -40 to 85 |
| 中文描述： | 四米的SRAM（512 - KWord的× 8位） |
| 文件頁數： | 5/17頁 |
| 文件大小： | 77K |
| 代理商： | HM62V8512B |
HM62V8512B Series
5
Function Table
WE
CS
OE
Mode
V
CC
current
I
SB
, I
SB1
I
CC
I
CC
I
CC
I
CC
Dout pin
Ref. cycle
×
H
×
Not selected
High-Z
—
H
L
H
Output disable
High-Z
—
H
L
L
Read
Dout
Read cycle
L
L
H
Write
Din
Write cycle (1)
L
Note:
L
L
Write
Din
Write cycle (2)
×
: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage
V
CC
V
T
P
T
Topr
–0.5 to +4.6
V
Voltage on any pin relative to V
SS
Power dissipation
–0.5*
1
to V
CC
+ 0.5*
2
1.0
V
W
Operating temperature
–20 to +70
°
C
°
C
°
C
Storage temperature
Tstg
–55 to +125
Storage temperature under bias
Notes: 1. –3.0 V for pulse half-width
≤
30 ns
2. Maximum voltage is 4.6 V
Tbias
–20 to +85
Recommended DC Operating Conditions
(Ta = –20 to +70
°
C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
V
SS
V
IH
V
IL
2.7
3.0
3.6
V
0
0
0
V
Input high voltage
2.0
—
V
CC
+ 0.3
0.8
V
Input low voltage
Note:
1. –3.0 V for pulse half-width
≤
30 ns
–0.3*
1
—
V
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