參數(shù)資料
型號(hào): HM62V8512B
廠商: Hitachi,Ltd.
英文描述: Quadruple Bus Buffer Gate With 3-State Outputs 14-SOIC -40 to 85
中文描述: 四米的SRAM(512 - KWord的× 8位)
文件頁(yè)數(shù): 7/17頁(yè)
文件大?。?/td> 77K
代理商: HM62V8512B
HM62V8512B Series
7
AC Characteristics
(Ta = –20 to +70
°
C, V
CC
= 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
Input pulse levels: 0.4 V to 2.4 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.4 V
Output timing reference level: 1.5 V/1.5 V(HM62V8512B-7)
0.8 V/2.0 V(HM62V8512B-8)
Output load: 1 TTL Gate + C
L
(50 pF)
(Including scope & jig)
Read Cycle
HM62V8512B
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read cycle time
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
70
85
ns
Address access time
70
85
ns
Chip select access time
70
85
ns
Output enable to output valid
35
45
ns
Chip selection to output in low-Z
10
10
ns
2
Output enable to output in low-Z
5
5
ns
2
Chip deselection to output in high-Z
0
30
0
35
ns
1, 2
Output disable to output in high-Z
0
30
0
35
ns
1, 2
Output hold from address change
10
10
ns
相關(guān)PDF資料
PDF描述
HM62V8512BLRR-7SL 4 M SRAM (512-kword x 8-bit)
HM62V8512BLRR-7UL 4 M SRAM (512-kword x 8-bit)
HM62V8512BLRR-8 4 M SRAM (512-kword x 8-bit)
HM62V8512BLRR-8SL 4 M SRAM (512-kword x 8-bit)
HM62V8512BLTT-7 4 M SRAM (512-kword x 8-bit)
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