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參數(shù)資料
| 型號： | HS1-82C37ARH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類： | DMA控制器 |
| 英文描述： | Radiation Hardened CMOS High Performance Programmable DMA Controller |
| 中文描述： | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, CDIP40 |
| 封裝： | METAL SEALED, SIDE BRAZED, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 253K |
| 代理商： | HS1-82C37ARH-Q |
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HS-82C37ARH
Note that the data is transferred directly from the I/O device
to memory (or vice versa) with IOR and MEMW (or MEMR
and IOW) being active at the same time. The data is not read
into or driven out of the HS-82C37ARH in I/O-to-memory or
memory-to-I/O DMA transfers.
Memory-to-Memory transfers require a read-from and a
write-to-memory to complete each transfer. The states,
which resemble the normal working states, use two-digit
numbers for identification. Eight states are required for a sin-
gle transfer. The first four states (S11, S12, S13, S14 are
used for the read-from-memory half and the last four states
(S21, S22, S23, S24) for the write-to-memory half of the
transfer.
Idle Cycle
When no channel is requesting service, the HS-82C37ARH
will enter the Idle cycle and perform “SI” states. In this cycle,
the HS-82C37ARH will sample the DREQ lines on the falling
edge of every clock cycle to determine if any channel is
requesting a DMA service.
Note that for standby operation where the clock has been
stopped, DMA requests will be ignored. The device will
respond to CS (chip select), in case of an attempt by the
microprocessor to write or read the internal registers of the
HS-82C37ARH. When CS is low and HLDA is low, the HS-
82C37ARH enters the Program Condition. The CPU can
now establish, change or inspect the internal definition of the
part by reading from or writing to the internal registers.
The HS-82C37ARH may be programmed with the clock
stopped, provided that HLDA is low and at least one rising
clock edge has occurred after HLDA was driven low, so the
controller is in an SI state. Address lines A0-A3 are inputs to
the device and select which registers will be read or written.
The IOR and IOW lines are used to select and time the read
or write operations. Due to the number and size of the inter-
nal registers, an internal flip-flop is used to generate an addi-
tional bit of address. The bit is used to determine the upper
or lower byte of the 16-bit Address and Word Count Regis-
ters. The flip-flop is reset by Master Clear or Reset. Separate
software commands can also set or reset this flip-flop.
Special software commands can be executed by the HS-
82C37ARH in the Program Condition. These commands are
decoded as sets of addresses with CS, IOR, and IOW. The
commands do not make use of the data bus. Instructions
include Set and Clear First/Last Flip-Flop, Master Clear,
Clear Mode Register Counter, and Clear Mask Register.
Active Cycle
When the HS-82C37ARH is in the Idle cycle, and a software
request or an unmasked channel requests a DMA service,
the device will output an HRQ to the microprocessor and
enter the Active cycle. It is in this cycle that the DMA service
will take place, in one of four modes:
Single Transfer Mode
- In Single Transfer mode, the device
is programmed to make one transfer only. The word count
will be decremented and the address decremented or incre-
mented following each transfer. When the word count “rolls
over” from zero to FFFFH, a terminal count (TC) bit in the
Status Register is set, an EOP pulse is generated, and the
channel will Autoinitialize if this option has been selected. If
not programmed to Autoinitialize, the mask bit will be set,
along with the TC bit and EOP pulse.
DREQ must be held active until DACK becomes active. If
DREQ is held active throughout the single transfer (there-by
triggering a second transfer), HRQ will still go inactive and
release the bus to the system. Then it will again go active
and, upon receipt of a new HLDA, another single transfer will
be performed, unless a higher priority channel takes over. In
HS-80C85RH or HS-80C86RH systems, this will ensure one
full machine cycle execution between DMA transfers. Details
of timing between the HS-82C37ARH and other bus control
protocols will depend upon the characteristics of the micro-
processor involved.
Block Transfer Mode
- In Block Transfer Mode, the device
is activated by DREQ or software request and continues
making transfers during the service until a TC, caused by
word count going to FFFFH, or an external End of Process
(EOP) is encountered. DREQ need only beheld active until
DACK becomes active. Again, an Autoinitialization will occur
at the end of the service if the channel has been pro-
grammed for that option.
Demand Transfer Mode
- In Demand Transfer Mode the
device continues making transfers until a TC or external
EOP is encountered, or until DREQ goes inactive. Thus,
transfers may continue until the I/O device has exhaust edits
data capacity. After the I/O device has had a chance to catch
up, the DMA service is reestablished by means of a DREQ.
During the time between services when the micro-processor
is allowed to operate, the intermediate values of address
and word count are stored in the HS-82C37ARH Current
Address and Current Word Count Registers. Higher priority
channels may intervene in the demand process, once DREQ
has gone inactive. Only an EOP can cause an Autoinitializa-
tion at the end of the service. EOP is generated either by TC
or by an external signal.
Cascade Mode
- This mode is used to cascade more than
one HS-82C37ARH for simple system expansion. The HRQ
and HLDA signals from the additional HS-82C37ARH are
connected to the DREQ and DACK signals respectively of a
channel for the initial HS-82C37ARH. This allows the DMA
requests of the additional device to propagate through the
priority network circuitry of the preceding device. The priority
chain is preserved and the new device must wait for its turn
to acknowledge requests. Since the cascade channel of the
initial HS-82C37ARH is used only for prioritizing the addi-
tional device, it does not output an address or control signals
of its own so that there is no conflict with the cascaded
device. The HS-82C37ARH will respond to DREQ and gen-
erate DACK but all other outputs except HRQ will be dis-
abled. An external EOP will be ignored by the initial device,
but will have the usual effect on the added device.
Figure 9 shows two additional devices cascaded with an ini-
tial device using two of the previous channels. This forms a
two-level DMA system. More HS-82C37ARHs could be
added at the second level by using the remaining channels
of the first level. Additional devices can also be added by
cascading into the channels of the second level devices,
forming a third level.
Spec Number
518058
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| HS-82C12 | Radiation Hardened 8-Bit Input/Output Port |
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| HS9-82C37ARH-Q | Radiation Hardened CMOS High Performance Programmable DMA Controller |
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相關代理商/技術參數(shù) |
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| HS1-82C37ARH-SAMPLE | 制造商:HARRIS 制造商全稱:HARRIS 功能描述:Radiation Hardened CMOS High Performance Programmable DMA Controller |
| HS1-82C52RH-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| HS1-82C54RH | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened CMOS Programmable Interval Timer |
| HS1-82C54RH/PROTO | 制造商:Intersil Corporation 功能描述:RAD HARD CMOS PROGRAMMABLE INTERVAL TIMER,PROTO,CLASS V - Rail/Tube |
| HS1-82C54RH-8 | 制造商:Intersil Corporation 功能描述:PROGRAMMABLE TIMER SGL 24PIN SBDIP - Rail/Tube |
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