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參數(shù)資料
| 型號： | HS1-82C37ARH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類： | DMA控制器 |
| 英文描述： | Radiation Hardened CMOS High Performance Programmable DMA Controller |
| 中文描述： | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, CDIP40 |
| 封裝： | METAL SEALED, SIDE BRAZED, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大小： | 253K |
| 代理商： | HS1-82C37ARH-Q |
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7
Specifications HS-82C37ARH
DMA (MASTER) MODE (Continued)
DB Float to Active Delay from
CLK HIGH
TCHDV
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
110
ns
HLDA Valid to CLK HIGH Setup
Time
TRAVCH
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
75
-
ns
Input Data from MEMR HIGH
Hold Time
TMRHDX
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
0
ns
Input Data to MEMR HIGH
Setup Time
TDVMRH
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
155
ns
Output Data from MEMW HIGH
HOLD Time
TMWHDZ
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
15
ns
Output Data Valid to MEMW
HIGH
TDVMWH
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
TCLCL-
35
-
ns
DREQ to CLK LOW (SI, S4)
Setup Time
TDQVCL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
0
-
ns
CLK LOW to READY Hold Time
TCLRYX
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
20
-
ns
READY to CLK LOW Setup
Time
TRYVCL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
60
-
ns
ADSTB HIGH from CLK LOW
Delay Time
TCLSH
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
80
ns
ADSTB LOW from CLK LOW
Delay Time
TCLSL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
120
ns
READ HIGH Delay fromWRITE
HIGH
TWHRH
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
0
-
ns
READ Pulse Width, Normal
Timing
TRLRH1
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
2TCLCL
-50
-
ns
ADSTB Pulse Width
TSHSL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
TCLCL -
80
-
ns
Extended WRITE Pulse Width
TWLWH1
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
2TCLCL
-100
-
ns
WRITE Pulse Width
TWLWH2
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
TCLCL -
100
-
ns
READ Pulse Width,
Compressed
TRLRH2
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
TCLCL -
50
-
ns
PERIPHERAL (SLAVE) MODE
ADR Valid or CS LOW to IOR
LOW
TAVIRL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
10
-
ns
ADR Valid or CS LOW to IOW
LOW Setup Time 0
TAVIWL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
0
-
ns
Data Valid to IOW HIGH Setup
Time
TDVIWH
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
150
-
ns
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
VCC = +5V
±
10%, GND = 0V, AC’s Tested at Worst Case VDD, Guaranteed Over Full Operating Range.
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
TEMPERATURE
SUBGROUP
LIMITS
UNITS
MIN
MAX
Spec Number
518058
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| HS-82C12 | Radiation Hardened 8-Bit Input/Output Port |
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| HS1-82C37ARH | Radiation Hardened CMOS High Performance Programmable DMA Controller |
| HS9-82C37ARH-Q | Radiation Hardened CMOS High Performance Programmable DMA Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HS1-82C37ARH-SAMPLE | 制造商:HARRIS 制造商全稱:HARRIS 功能描述:Radiation Hardened CMOS High Performance Programmable DMA Controller |
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| HS1-82C54RH | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened CMOS Programmable Interval Timer |
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