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參數(shù)資料
| 型號： | HSP43216VC-52Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HALFBAND FILTER 100-MQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 濾波器類型： | 半帶 |
| 濾波器數(shù)： | 4 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-MQFP（14x20） |
| 包裝： | 托盤 |
10
FN3365.10
October 6, 2008
In the polyphase implementation, the input data stream
feeds even and odd tap filters running at the input sample
rate. The interpolated sample stream is derived by
multiplexing the output of each polyphase branch into a
single data stream at twice the input sample rate. As in the
Decimate by Two example, the even or odd tap filters are
comprised of the even or odd indexed coefficients from the
original transversal filter.
The operation of the HSP43216 in Interpolate by Two mode
is analogous to the polyphase example above. In this mode
the internal data flow is routed as shown in Figure 11A and
Figure 11B. The different data flows depend on the selection
of internal or external multiplexing via INT/EXT. In this mode,
data input through AIN0-15 is fed to the even and odd
polyphase branches of the filter processor. The output of
each branch is multiplexed together to generate the output
data stream at the interpolated rate. NOTE: The output of
each polyphase branch is scaled by two to compensate
for the attenuation of one half caused by interpolation.
C0 C1 C2 C3 C4 C5 C6
..,X2,X1,X0
Y(1) = X0(C0)+0(C1)+X1(C2)+0(C3)+X2(C4)+0(C5)+X3(C6)
Y(0) = 0(C0)+X0(C1)+0(C2)+X1(C3)+0(C4)+X2(C5)+0(C6)
...,Y1,Y0
2
..X1,0,X0,0
7 TAP HALFBAND FILTER
Y(3) = X1(C0)+0(C1)+X2(C2)+0(C3)+X3(C4)+0(C5)+X4(C6)
Y(2) = 0(C0)+X1(C1)+0(C2)+X2(C3)+0(C4)+X3(C5)+0(C6)
FIGURE 9. TRANSVERSAL IMPLEMENTATION OF
INTERPOLATE BY TWO HALFBAND FILTER
C0 C2 C4 C6
...,X2,X1,X0
Y0 = X0(C1)+X1(C3)+X2(C5)
Y1 = X0(C0)+X1(C2)+X2(C4)+X3(C6)
..,Y4,Y2,Y0
C1 C3 C5
R
E
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ODD TAP FILTER
EVEN TAP FILTER
M
U
X
..,Y5,Y3,Y1
..,Y2,Y1,Y0
Y2 = X1(C1)+X2(C3)+X3(C5)
FIGURE 10. POLYPHASE IMPLEMENTATION OF
INTERPOLATE BY TWO HALFBAND FILTER
FIGURE 11A. DATA FLOW DIAGRAM FOR INTERPOLATE BY 2 FILTER MODE (INT/EXT = 1)
FIGURE 11B. DATA FLOW DIAGRAM FOR INTERPOLATE BY 2 FILTER MODE (INT/EXT = 0)
EVEN TAP
FILTER
ODD TAP
FILTER
AIN0-15
AOUT0-15
OEA
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1
2
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Clocked at CLK/2
GROUP DELAY 19
PIPELINE DELAY 2-35
PIPELINE DELAY 19
EVEN TAP
FILTER
AIN0-15
AOUT0-15
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ODD TAP
FILTER
OEB
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BOUT0-15
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OEA
GROUP DELAY 19
PIPELINE DELAY 2-35
GROUP DELAY 19
PIPELINE DELAY 19
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HSP43216
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相關(guān)代理商/技術(shù)參數(shù) |
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