- 您現在的位置：買賣IC網 > PDF目錄371896 > HSP43220JC-15 (INTERSIL CORP) Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:4; Connector Shell Size:24; Connecting Termination:Solder; Circular Shell Style:Box Mount Receptacle; Body Style:Straight PDF資料下載
參數資料
| 型號： | HSP43220JC-15 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:4; Connector Shell Size:24; Connecting Termination:Solder; Circular Shell Style:Box Mount Receptacle; Body Style:Straight |
| 中文描述： | 16-BIT, DSP-DIGITAL FILTER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數： | 5/19頁 |
| 文件大?。?/td> | 190K |
| 代理商： | HSP43220JC-15 |
3-198
The HDF
The first filter section is called the High Order Decimation Filter
(HDF) and is optimized to perform decimation by large factors.
It implements a low pass filter using only adders and delay
elements instead of a large number of multiplier/ accumulators
that would be required using a standard FIR filter.
The HDF is divided into 4 sections: the HDF filter section,
the clock divider, the control register logic and the start logic
(Figure 1).
Data Shifter
After being latched into the Input Register the data enters the
Data Shifter. The data is positioned at the output of the shifter
to prevent errors due to overflow occurring at the output of the
HDF. The number of bits to shift is controlled by H_GROWTH.
Integrator Section
The data from the shifter goes to the Integrator section.
This is a cascade of 5 integrator (or accumulator) stages,
which implement a low pass filter. Each accumulator is
implemented as an adder followed by a register in the feed
forward path. The integrator is clocked by the sample clock,
CK_IN as shown in Figure 2. The bit width of each integrator
stage goes from 66 bits at the first integrator down to 26 bits
at the output of the fifth integrator. Bit truncation is performed
at each integrator stage because the data in the integrator
stages is being accumulated and thus is growing, therefore
the lower bits become insignificant, and can be truncated
without losing significant data.
A0, A1
I
Control Register Address. These lines are decoded to determine which control register is the destination for the data on
C_BUS0-15. Register loading is controlled by the A0 and A1, WR and CS inputs.
ASTARTIN
I
ASTARTIN is an asynchronous signal which is sampled on the rising edge of CK_IN. It is used to put the DDF in operational
mode. ASTARTIN is internally synchronized to CK_IN and is used to generate STARTOUT.
STARTOUT
O
STARTOUT is a pulse generated from the internally synchronized version of ASTARTIN. It is provided as an output for use
in multi-chip configurations to synchronously start multiple HSP43220's. The width of STARTOUT is equal to the period of
CK_IN.
STARTIN
I
STARTIN is a Synchronous Input. A high to low transition of this signal is required to start the part. STARTIN is sampled on
the rising edge of CK_IN. This synchronous signal can be used to start single or multiple HSP43220's.
OUT_SELH
I
Output Select. The OUT_SELH input controls which bits are provided at output pins DATA_OUT16-23. A HIGH on this control
line selects bits 28 through 21 from the accumulator output. A LOW on this control line selects bits 2-16 through 2-23 from
the accumulator output. Processing is not interrupted by this pin.
OUT_ENP
I
Output Enable. The OUT_ENP input controls the state of the lower 16 bits of the output data bus, DATA_OUT0-15. A LOW on
this control line enables the lower 16 bits of the output bus. When OUT_ENP is HIGH, the output drivers are in the high imped-
ance state. Processing is not interrupted by this pin.
OUT_ENX
I
Output Enable. The OUT_ENX input controls the state of the upper 8 bits of the output data bus, DATA_OUT16-23. A LOW
on this control line enables the upper 8 bits of the output bus. When OUT_ENX is HIGH, the output drivers are in the high
impedance state. Processing is not interrupted by this pin.
Pin Description
(Continued)
NAME
TYPE
DESCRIPTION
FIGURE 1. HIGH ORDER DECIMATION FILTER FIGURE
HDF FILTER SECTION
DEC
REG
INTEGRATOR
INPUT
REG
COMB FILTER
ROUND
REG
26
16
TO FIR
16
19
26
66
16
16
ISTART
COMB_EN1-5
H_GROWTH
INT_EN1-5
RESET
RESET
5
CK_IN
CK_DEC
TO FIR
STARTIN
STARTOUT
START
LOGIC
RESET
ASTARTIN
CK_IN
DATA
IN
ISTART
RESET
H_DRATE
H_BYP
CK_IN
CLOCK
DIVIDER
CONTROL
REGISTER LOGIC
A0-1
WR
CS
C_BUS
COMB_EN1-5
6
5
5
H_GROWTH
INT_EN1-5
CK DEC
5
6
DATA
SHIFTER
HSP43220
相關PDF資料 |
PDF描述 |
|---|---|
| HSP43220GC-25 | Decimating Digital Filter |
| HSP43220GC-33 | Decimating Digital Filter |
| HSP43220VC-33 | Decimating Digital Filter |
| HSP43220 | RESISTOR 47 OHM 20W TO220 |
| HSP43220883 | Decimating Digital Filter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HSP43220JC-25 | 功能描述:有源濾波器 DECIMATING DIGITAL FILTER 84 PLCC, 25.6MHZ, COMM RoHS:否 制造商:Maxim Integrated 通道數量:1 截止頻率:150 KHz 電源電壓-最大:11 V 電源電壓-最小:4.74 V 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP N 封裝:Tube |
| HSP43220JC-25Z | 功能描述:有源濾波器 W/ANNEAL DECIMATING DIGTL FILTER 6MHZ RoHS:否 制造商:Maxim Integrated 通道數量:1 截止頻率:150 KHz 電源電壓-最大:11 V 電源電壓-最小:4.74 V 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP N 封裝:Tube |
| HSP43220JC-33 | 功能描述:有源濾波器 DECIMATING DIGITAL FILTER 84 PLCC, 33MHZ RoHS:否 制造商:Maxim Integrated 通道數量:1 截止頻率:150 KHz 電源電壓-最大:11 V 電源電壓-最小:4.74 V 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP N 封裝:Tube |
| HSP43220JC-33Z | 功能描述:有源濾波器 W/ANNEAL DECIMATING DIGTL FILTER 33MHZ RoHS:否 制造商:Maxim Integrated 通道數量:1 截止頻率:150 KHz 電源電壓-最大:11 V 電源電壓-最小:4.74 V 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP N 封裝:Tube |
| HSP43220TM-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
發(fā)布緊急采購，3分鐘左右您將得到回復。