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參數(shù)資料
| 型號(hào)： | HSP43220JC-33 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | CONNECTOR: SECURE DIGITAL MEMORY CARD |
| 中文描述： | 16-BIT, DSP-DIGITAL FILTER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 190K |
| 代理商： | HSP43220JC-33 |
3-201
FC_Register (A1 = 0, A0 = 1)
FIGURE 5.
H_Register 1 (A1 = 1, A0 = 0)
FIGURE 6.
DDF Control Registers
(Continued)
F_CF
C19 C18 C17 C16 C15 C14 C13 C12 C11 C10
C9
C8
C7
C6
C5
C4
X
X
X
X
X
X
X
X
X
X
X
X
C3
C2
C1
C0
F_CF
Bits C0-C19 represent the coefficient data, where C19 is the MSB. Two writes are
required to write each coefficient which is 2's complement fractional format. The first
write loads C19 through C4; C3 through C0 are loaded on the second write cycle. As
the coefficients are written into this register they are formatted into a 20-bit coefficient
and written into the Coefficient RAM sequentially starting with address location zero.
The coefficients must be loaded sequentially, with the center tap being the last coeffi-
cient to be loaded. See coefficient RAM, below.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
F_DIS
F_CLA
H_BYP
H_DRATE
FD0
FC0
HB0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
H_DRATE Bits
R0-R9 are used to select the amount of decimation in the HDF. The amount of deci-
mation selected is programmed as the required decimation minus one; for instance
to select decimation of 1024 H_DRATE is set equal to 1023. HDRATE +1 is defined
as H
DEC
.
H_BYP
Bit HB0 is used to select HDF bypass mode. This mode is selected by setting H_BYP =
1. When this mode is selected the input data passes through the HDF unfiltered. Inter-
nally H_STAGES and H_DRATE are both set to zero and H_GROWTH is set to 50.
H_REGISTER 2 must be reloaded when H_BYP is returned to 0. To disable HDF
bypass mode H_BYP = 0. The relationship between CK_IN and FIR_CK in this and all
other modes is defined by Equation 1.
F_CLA
Bit FC0 is used to select the clear accumulator mode in the FIR. This mode is enabled
by setting F_CLA = 1 and is disabled by setting F_CLA = 0. In normal operation this bit
should be set equal to zero. This mode zeros the feedback path in the accumulator of
the multiplier/accumulator (MAC). It also allows the multiplier output to be clocked off
the chip by FIR_CK, thus DATA_RDY has no meaning in this mode. This mode can be
used in conjunction with the F_OAD bit to read out the FIR coefficients from the coeffi-
cient RAM.
F_DIS
Bit FD0 is used to select the FIR disable mode. This feature enables the FIR parame-
ters to be changed. This feature is selected by setting F_DIS = 1. This mode termi-
nates the current FIR cycle. While this feature is selected, the HDF continues to
process data and write it into the FIR data RAM. When the FIR re-programming is
completed, the FIR can be re-enabled either by clearing F_DIS, or by asserting one of
the start inputs, which automatically clears F_DIS.
HSP43220
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| HSP43220JC-33Z | 功能描述:有源濾波器 W/ANNEAL DECIMATING DIGTL FILTER 33MHZ RoHS:否 制造商:Maxim Integrated 通道數(shù)量:1 截止頻率:150 KHz 電源電壓-最大:11 V 電源電壓-最小:4.74 V 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP N 封裝:Tube |
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| HSP43220TM-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
| HSP43220VC-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
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