Confidential
HV7131R
Register Description
Register
Device ID
This document is a general product description and is subject to change without notice. MagnaChip
Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent
licenses are implied.
- 11 -
2004 MagnaChip Semiconductor Ltd.
Symbol Address Default
DEVID
00h
Description
Identification,
02h
Product
Number.
ClkDiv[6:4],
XFlip[1], YFlip[0]
VCLK Disable[6], ADCPwDn[5], Black
Mode[4],
Sleep[3],
BLDataEn[1], StrobeEn[0]
ByrDpcEn[6],
ClkHSC[3],
InvVSC[2],
InvVCLK[0]
Row Start Address Upper Byte[8]
Row Start Address Lower Byte[7:0]
Column Start Address Upper Byte[9:8]
Column Start Address Lower Byte[7:0]
Window Height Upper Byte[8]
Window Height Lower Byte[7:0]
Window Width Upper Byte[9:8]
Window Width Lower Byte[7:0]
HBLANK Time Upper Byte[15:8].
HBLANK Time Lower Byte[7:0].
VBLANK Time Upper Byte[15:8].
VBLANK Time Lower Byte[7:0].
Integration Time [23:16]
Revision
Sensor Control A
SCTRA
01h
09h
ABLCEn[3],
PxlVs[2],
Sensor Control B
SCTRB
02h
01h
VsHsEn[2],
Output Inversion
OUTIV
03h
00h
ByrDpcTh[5:4],
InvHSC[1],
Row Start Add Upper
Row Start Add Lower
Col. Start Add Upper
Col. Start Add Lower
Window Height Upper
Window Height Lower
Window Width Upper
Window Width Lower
HBLANK Time Upper
HBLANK Time Lower
VBLANK Time Upper
VBLANK Time Lower
Integration Time High
Integration
Middle
Integration Time Low
RSAU
RSAL
CSAU
CSAL
WIHU
WIHL
WIWU
WIWL
HBLU
HBLL
VBLU
VBLL
INTH
10h
11h
12h
13h
14h
15h
16h
17h
20h
21h
22h
23h
25h
00h
02h
00h
02h
01h
e2h
02h
82h
00h
d0h
00h
08h
06h
Time
INTM
26h
5Bh
Integration Time [15:8]
INTL
27h
9ah
Integration Time [7:0]
Gain for Pre-amp (0.5~16.5 times with
8bit resolution) [7:0]
Gain for Red Pixel Read-out (0.5~2
times with 6bit resolution) [5:0]
Gain for Green Pixel Read-out (0.5~2
times with 6bit resolution [5:0]
Gain for Blue Pixel Read-out (0.5~2
times with 6bit resolution [5:0]
Pre-amp Gain
PAG
30h
10h
Red Color Gain
RCG
31h
10h
Green Color Gain
GCG
32h
10h
Blue Color Gain
BCG
33h
10h
Analog Bias Control A
ACTRA
34h
17h
CDS Bias [6:4], PGA Bias [3:0]
Analog Bias Control B
ACTRB
35h
7fh
Reset Clamp [7:4], ADC Bias [3:0]
Auto Black Level Pixel Threshold
Value
Initial ADC Offset Red
Black Level Threshold
BLCTH
40h
ffh
Initial ADC Offset Red
Initial
ADC
Green
Initial ADC Offset Blue
ORedI
41h
7fh
Offset
OGrnI
42h
7fh
Initial ADC Offset Green
OBluI
43h
7fh
Initial ADC Offset Blue