參數(shù)資料
型號: HV7131R
廠商: Electronic Theatre Controls, Inc.
元件分類: 圖像傳感器
英文描述: CMOS Image Sensor
中文描述: CMOS圖像傳感器
文件頁數(shù): 13/33頁
文件大?。?/td> 1481K
代理商: HV7131R
Confidential
HV7131R
This document is a general product description and is subject to change without notice. MagnaChip
Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent
licenses are implied.
- 13 -
2004 MagnaChip Semiconductor Ltd.
7
6
5
4
3
2
1
0
Reserved
VCLK
ADC
PwDn
Black
Mode
Sleep
Mode
VsHsEn
BLDataEn
StrobeEn
-
0
0
0
0
0
0
1
VCLK
When this bit is high Video Output Clock(VCLK) Disable
ADCPwDn
When this bit is high ADC Block goes to Power Down
Black Mode
Black and White Mode : Red and Blue gain use the Green gain when this bit is set to high.
0 : Color Mode
1 : Black and White Mode
Sleep Mode
Software Power Down
0 : Software power down mode off.
1 : Software power down mode on.
All internal digital block goes to sleep mode with this bit set to high
VsHsEn
HSYNC in VBLANK : VBLANK is equivalent to VSYNC, and HSYNC is the inversion of
HBLANK, and this signal control whether HSYNC is active or not when VBLANK unit is LCF.
0 : There are no valid HSYNC signals during valid VSYNC signal.
1 : There are valid HSYNC signals during valid VSYNC signal. Number of valid HSYNC is
same as number of VBLANK register when VSYNC unit is line unit. Do not use this mode
when VSYNC unit is pixel unit
VSYNC
(VBLANK)
HSYNC
BLDataEn
Black Level Data Enable : HSYNC is generated for light-shielded pixels in 4 lines.
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