參數(shù)資料
型號: HY27SS08121M
廠商: Hynix Semiconductor Inc.
英文描述: 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
中文描述: 512兆(64Mx8bit / 32Mx16bit)NAND閃存
文件頁數(shù): 29/43頁
文件大?。?/td> 729K
代理商: HY27SS08121M
Rev 0.6 / Oct. 2004
29
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 15: AC Characteristics for Operation (3.3V Device and 1.8V Device)
Alt.
Sym-
bol
Sym-
bol
Parameter
3.3V
Device
1.8V
Device
Unit
t
ALLRL1
t
AR1
Address Latch Low to Read Enable
Low
Read Electronic Signature
Min
10
25
ns
t
ALLRL2
t
AR2
Read cycle
Min
50
80
ns
t
BHRL
t
RR
Ready/Busy High to Read Enable Low
Min
20
ns
t
BLBH1
t
R
Ready/Busy Low to Ready/Busy High
Read Busy time, 512Mb, 1Gb
4)
Max
12
15
us
t
BLBH2
t
PROG
Program Busy time
Max
500
us
t
BLBH3
t
BERS
Erase Busy time
Max
3
ms
t
BLBH4
t
RST
Reset Busy time, during ready
Max
5
us
Reset Busy time, during read
Max
5
us
Reset Busy time, during program
Max
10
us
Reset Busy time, during erase
Max
500
us
t
CLLRL
t
CLR
Command Latch Low to Read Enable Low
Min
10
ns
t
DZRL
t
IR
Data Hi-Z to Read Enable Low
Min
0
ns
t
EHBH
t
CRY
Chip Enable High to Ready/Busy High (CE intercepted read)
Max
70+tr
(1)
ns
t
EHEL
t
CEH
Chip Enable High to Chip Enable Low
(2)
Min
100
ns
t
EHQZ
t
CHZ
Chip Enable High to Output Hi-Z
Max
20
ns
t
ELQV
t
CEA
Chip Enable Low to Output Valid
Max
45
75
ns
t
RHBL
t
RB
Read Enable High to Ready/Busy Low
Max
100
ns
t
RHRL
t
REH
Read Enable High to Read Enable
Low
Read Enable High Hold time
Min
15
20
ns
t
RHQZ
t
RHZ
Read Enable High to Output Hi-Z
Min
15
ns
Max
30
t
RLRH
t
RP
Read Enable Low to Read Enable
High
Read Enable Pulse Width
Min
30
60
ns
t
RLRL
t
RC
Read Enable Low to Read Enable Low
Read Cycle time
Min
50
80
ns
t
RLQV
t
REA
Read Enable Low to Output Valid
Read Enable Access time
Max
35
60
ns
t
READID
Read ES Access time
45
t
WHBH
t
R
Write Enable High to Ready/Busy High
Max
12
15
us
t
WHBL
t
WB
Write Enable High to Ready/Busy Low
Max
100
ns
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