參數(shù)資料
型號: HY27SS561M
廠商: Hynix Semiconductor Inc.
英文描述: 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
中文描述: 片256Mbit(32Mx8bit / 16Mx16bit)NAND閃存
文件頁數(shù): 15/44頁
文件大?。?/td> 733K
代理商: HY27SS561M
Rev 0.7 / Oct. 2004
15
HY27SS(08/16)561M Series
HY27US(08/16)561M Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Note:
1. If t
ELWL
is less than 10ns, t
WLWH
must be minimum 35ns, otherwise, t
WLWH
may be minimum 25ns.
Note: 1. Highest address depends on device density.
Figure 10. Read (A, B, C) Operation
Figure 11. Read Block Diagrams
CLE
ALE
I/O
RB
tBLBH1
(read)
00h/
01h/ 50h
Command
Code
Address Input
Data Output (sequentially)
Busy
CE
WE
RE
Area A
(1st half Page)
Area B
(2nd half
Page)
Area C
(Spare)
Read A Command, x8 Devices
A9-A24(1)
A0-A7
Area C
(50h)
Read A Command, x16 Devices
Area A
(main area)
A9-A24(1)
A0-A7
Area A
Area C
(Spare)
Read C Command, x8/x16 Devices
A9-A24(1)
A0-A3 (x8)
A0-A2 (x16)
Area A/B
A4-A7 (x8), A3-A7 (x16) are don't care
Area A
(1st half Page)
Area C
(Spare)
Read B Command, x8 Devices
A9-A24(1)
A0-A7
Area B
(2nd half
Page)
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