參數(shù)資料
型號： HY27SS561M
廠商： Hynix Semiconductor Inc.
英文描述： 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
中文描述： 片256Mbit（32Mx8bit / 16Mx16bit）NAND閃存
文件頁數(shù)： 9/44頁
文件大?。?/td> 733K
代理商： HY27SS561M
Rev 0.7 / Oct. 2004
9
HY27SS(08/16)561M Series
HY27US(08/16)561M Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the Program/ Erase/ Read (PER)
Controller is currently active.
When Ready/Busy is Low, V
OL
, a read, program or erase operation is in progress. When the operation completes
Ready/Busy goes High, V
OH
.
The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-
up resistor. A Low will then indicate that one, or more, of the memories is busy.
Refer to the Ready/Busy Signal Electrical Characteristics section for details on how to calculate the value of the pull-up
resistor.
V
CC
Supply Voltage
V
CC
provides the power supply to the internal core of the memory device. It is the main power supply for all operations
(read, program and erase).
An internal voltage detector disables all functions whenever V
CC
is below 2.0V (for 3.3V devices) or 1.5V (for 1.8V
devices) to protect the device from any involuntary program/erase during power-transitions.
Each device in a system should have V
CC
decoupled with a 0.1uF capacitor. The PCB track widths should be sufficient
to carry the required program and erase currents
.
V
SS
Ground
Ground, V
SS
, is the reference for the power supply. It must be connected to the system ground.
GND
GND input for spare Area Enable.
If GND input pin connect to Vss or static low state, the sequential read including spare area is possible.
But if GND input pin connect to Vcc or static high state, the sequential read excluding spare area is possible.
BUS OPERATIONS
There are six standard bus operations that control the memory. Each of these is described in this section, see Tables 2,
Bus Operations, for a summary.
Command Input
Command Input bus operations are used to give commands to the memory. Command are accepted when Chip Enable
is Low, Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High. They are latched on the
rising edge of the Write Enable signal.
Only I/O
0
to I/O
7
are used to input commands. See Figure 21 and Table 14 for details of the timings requirements.
Address Input
Address Input bus operations are used to input the memory address. Three bus cycles are required to input the
addresses for the 256Mb devices (refer to Tables 3 and 4, Address Insertion). The addresses are accepted when Chip
Enable is Low, Address Latch Enable is High, Command Latch Enable is Low and Read Enable is High. They are latched
on the rising edge of the Write Enable signal. Only I/O
0
to I/O
7
are used to input addresses.
See Figure 22 and Table 14 for details of the timings requirements.
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