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參數(shù)資料
| 型號： | HYB 314175BJ-50 |
| 廠商： | SIEMENS AG |
| 英文描述： | 3.3V 256 K x 16-Bit EDO-DRAM(3.3V 256K×16位 外延式數(shù)據(jù)輸出（EDO)動態(tài)RAM) |
| 中文描述： | 3.3V的256畝× 16位江戶的DRAM（3.3 256K × 16位外延式數(shù)據(jù)輸出（EDO公司）動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 1307K |
| 代理商： | HYB 314175BJ-50 |
Semiconductor Group
1
The HYB 314175BJ/BJL is the new generation dynamic RAM organized as 262 144 words by
16-bit. The HYB 314175BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit
techniques to provide wide operation margins, both internally and for the system user. Multiplexed
address inputs permit the HYB 314175BJ/BJL to be packed in a standard plastic 400mil wide
P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with
commonly used automatic testing and insertion equipment. System oriented features include Self
Refresh (L-Version), single + 3.3 V (
±
0.3 V) power supply, direct interfacing with high performance
logic device families.
3.3V 256 K x 16-Bit EDO-DRAM
3.3V 256 K x 16-Bit EDO-DRAM
(Low power version with Self Refresh)
Preliminary Information
262 144 words by 16-bit organization
0 to 70
°
C operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
55 ns (-55 version)
60 ns (-60 version)
CAS access time:
13ns (-50 & -55 version)
15 ns (-60 version)
Cycle time:
89 ns (-50 version)
94 ns (-55 version)
104 ns (-60 version)
Hype page mode (EDO) cycle time
20 ns (-50 & -55 version)
25 ns (-60 version)
High data rate
50 MHz (-50 & -55 version)
40 MHz (-60 version)
Single + 3.3 V (
±
0.3 V) supply with a built-
in VBB generator
Low Power dissipation
max. 450 mW active (-50 version)
max. 432 mW active (-55 version)
max. 378 mW active (-60 version)
Standby power dissipation
7.2 mW standby (TTL)
3.6 mW max. standby (CMOS)
0.72 mW max. standby (CMOS) for
Low Power Version
Output unlatched at cycle end allows two-
dimensional chip selection
Read, write, read-modify write, CAS-
before-RAS refresh, RAS-only refresh,
hidden-refresh and hyper page (EDO)
mode capability
2 CAS / 1 WE control
Self Refresh (L-Version)
All inputs and outputs TTL-compatible
512 refresh cycles / 16 ms
512 refresh cycles / 128 ms
Low Power Version only
Plastic Packages:
P-SOJ-40-1 400mil width
7.96
HYB 314175BJ-50/-55/-60
HYB 314175BJL-50/-55/-60
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB314175BJ-50- | High-Speed Fully-Differential Amplifiers 8-MSOP-PowerPAD -40 to 85 |
| HYB314175BJ-55 | High-Speed Fully-Differential Amplifiers 8-MSOP-PowerPAD -40 to 85 |
| HYB314175BJ-60 | Transistor Array IC; Package/Case:16-DIP; Mounting Type:Through Hole |
| HYB 314175BJ-55 | 3.3V 256 K x 16-Bit EDO-DRAM(3.3V 256K×16位 外延式數(shù)據(jù)輸出（EDO)動態(tài)RAM) |
| HYB 314175BJ-60 | 3.3V 256 K x 16-Bit EDO-DRAM(3.3V 256K×16位 外延式數(shù)據(jù)輸出（EDO)動態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB314175BJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM Low power version with Self Refresh |
| HYB314175BJ-50- | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM Low power version with Self Refresh |
| HYB314175BJ-55 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM Low power version with Self Refresh |
| HYB314175BJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM Low power version with Self Refresh |
| HYB314175BJL-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM Low power version with Self Refresh |
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